K6T1008C2C-DB70 Samsung, K6T1008C2C-DB70 Datasheet
K6T1008C2C-DB70
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K6T1008C2C-DB70 Summary of contents
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... K6T1008C2C Family Document Title 128K x8 bit Low Power CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 First revision - Seperate read and write Read : 15mA, Write : 35mA CC = CC1 1.0 Finalized - Add 70ns speed bin for commercial product and 85ns speed bin for industrial ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6T1008C2C families are fabricated by SAMSUNG s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The fami- lies also support low data retention voltage for battery back- up operation with low data retention current ...
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... K6T1008C2C Family PRODUCT LIST Commercial Temperature Products(0~70 C) Part Name K6T1008C2C-DL55 32-DIP, 55ns, L-pwr 32-DIP, 70ns, L-pwr K6T1008C2C-DL70 K6T1008C2C-DB55 32-DIP, 55ns, LL-pwr K6T1008C2C-DB70 32-DIP, 70ns, LL-pwr 32-SOP, 55ns, L-pwr K6T1008C2C-GL55 32-SOP, 70ns, L-pwr K6T1008C2C-GL70 32-SOP, 55ns, LL-pwr K6T1008C2C-GB55 32-SOP, 70ns, LL-pwr K6T1008C2C-GB70 ...
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... K6T1008C2C Family RECOMMENDED DC OPERATING CONDITIONS Item Symbol Supply voltage Ground Input high voltage Input low voltage Note 1. Commercial Product : and Industrial Product : Overshoot : Vcc+3.0V for 30ns pulse width. 3. Undershoot : -3.0V for 30ns pulse width. 4. Overshoot and undershoot are sampled, not 100% tested. ...
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... K6T1008C2C Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :C =100pF+1TTL L AC CHARACTERISTICS Parameter List Read cycle time Address access time ...
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... K6T1008C2C Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6T1008C2C Family TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address Data in Data out High-Z (WE Controlled CW( CW(2) t WP(1) t AS( Data Valid t WHZ (CS Controlled CW(2) AS( WP( Data Valid ...
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... K6T1008C2C Family TIMING WAVEFORM OF WRITE CYCLE(3) Address Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS CS going high and WE going low : A write end at the earliest transition among measured from the begining of write to the end of write. ...
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... K6T1008C2C Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) #32 13.60 0.20 0.535 0.008 #1 1. 0.075 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) #32 #1 20.87 0.822 20.47 0.806 +0.100 0.41 -0.050 0. +0.004 0.016 0.028 -0.002 42.31 MAX 1.666 41.91 0.20 1.650 0.008 0.46 0.10 0.018 0.004 1.52 2.54 0.10 0.060 0.100 0.004 #17 14.12 0.30 0.556 0.012 #16 2.74 0.20 MAX 0.108 0.008 3.00 0.118 0.20 0.008 1 ...
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... K6T1008C2C Family PACKAGE DIMENSIONS 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.50 0.0197 #16 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820R) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #16 0.50 0.0197 #1 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 10 CMOS SRAM ...