21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Functional Units
6.6.3
H_UBRLCR—Offset 168h
Writing to this register sets the bit rate and mode for the UART.
Dword Bit
Name
0
Break
1
Parity
enable
2
Odd/even
select
3
Stop bit
select
4
Enable FIFO
6:5
Data size
select
31:7
6-16
R/W
Description
R/W
When the break (BRK) bit is set, the UART first completes generation
and transmission of the frame currently being processed, stops
fetching data from the transmit FIFO, and forces the transmit pin low.
The transmit pin remains low until the BRK bit is cleared or a reset
occurs.
The break signal does not affect the receive portion of the FIFO, thus
normal operation on the receive line continues during the signaling of a
break.
R/W
The parity enable (PE) bit is used to enable or disable parity checking
by the receive data logic. Parity generation by the transmit logic is not
affected by the PE bit. When parity is enabled (PE = 1), the odd/even
parity select (OES) control bit is decoded to determine which type of
parity should be checked, and each piece of data placed within the
receive FIFO is checked. If the parity type programmed in the OES bit
does not match the parity of the data received, the data is tagged by
setting bit [8] of the FIFO location corresponding to the data that
provides the parity error.
R/W
The odd/even parity select (OES) bit is used to select whether odd or
even parity should be used by the transmit and receive logic. When
the OES is 1, even parity is selected; when the OES is 0, odd parity is
selected. The MSB in each frame is used as the parity bit. (The
transmit logic generates a parity bit by counting the number of ones
within the data to be transmitted, and sets the parity bit if the type of
parity selected matches the parity of the data. The receive data logic
strips the parity bit and counts the number of ones in the received data.
If the parity type of the data does not match the parity selected by
OES, the parity error status flag is set within the status register, as well
as bit [8] of the FIFO location corresponding to the data that produced
the parity error.)
R/W
The stop bit select (SBS) bit selects whether one or two stop bits
should be used in transmission. When SBS = 0, one stop bit is
inserted in the transmit frame for each character, and the receive data
logic looks for and strips one stop bit per character.
R/W
The enable FIFO (EF) bit is used to select whether the whole FIFO
should be used, or whether just the top-most entry should be used to
buffer both transmit and receive data. When EF = 1, all 16 entries in
both the transmit and the receive FIFO are used. When EF = 0, only
the top-most entries are used. The programming of this bit also affects
generation of the RXINT and TXINT interrupts. When only the top-
most entry is enabled, a service request is generated each time a
frame is received or transmitted. If the FIFO is filled halfway, 8 of 16
entries contain valid data.
R/W
Specifies the UART data length as follows:
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits
When this field is programmed to be less than eight bits, the data is
right justified in the FIFO, and the unused bits are zero filled.
R
Read only as 0.
21285 Core Logic for SA-110 Datasheet