VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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I/O Offset 2D-2C - Global Control (GBL_CTL) ............ RW
15-12 Reserved
........................................ always reads 0
11
IDE Secondary Bus Power-Off
0
Disable ...................................................default
1
Enable
10
IDE Primary Bus Power-Off
0
Disable ...................................................default
1
Enable
9
Reserved
........................................ always reads 0
8
SMI Active (INSMI)
0
SMI Inactive...........................................default
1
SMI Active. If the SMIIG bit is set, this bit
needs to be written with a 1 to clear it before
the next SMI can be generated.
7
LID Triggering Polarity
0
Rising Edge ............................................default
1
Falling Edge
6
THRM# Triggering Polarity
0
Rising Edge ............................................default
1
Falling Edge
5
Battery Low Resume Disable
0
Enable resume ........................................default
1
Disable
resume
BATLOW# is asserted
4
SMI Lock (SMIIG)
0
Disable SMI Lock
1
Enable SMI Lock (SMI low to gate for the
next SMI) ...............................................default
3
Wait for Halt / Stop Grant Cycle for CPUSTP#
Assertion
0
Don’t wait...............................................default
1
Wait
This bit works with Rx4C[7] of PCI configuration
space to control the start of CPUSTP# assertion.
2
Power Button Triggering Select
0
SCI/SMI generated by PWRBTN# rising edge
.....................................................default
1
SCI/SMI generated by PWRBTN# low level
Set to zero to avoid the situation where PB_STS is set
to wake up the system then reset again by
PBOR_STS to switch the system into the soft-off
state.
1
BIOS Release (BIOS_RLS)
This bit is set by legacy software to indicate release
of the SCI/SMI lock.
Upon setting of this bit,
hardware automatically sets the GBL_STS bit. This
bit is cleared by hardware when the GBL_STS bit
cleared by software.
Note that if the GBL_EN bit is set (bit-5 of the Power
Management Enable register at offset 2), then setting
this bit causes an SCI to be generated (because setting
this bit causes the GBL_STS bit to be set).
0
SMI Enable (SMI_EN)
0
Disable all SMI generation.....................default
1
Enable SMI generation
Revision 1.71 June 9, 2000
I/O Offset 2F - SMI Command (SMI_CMD) ................. RW
7-0
from
suspend
when
-95-
SMI Command
Writing to this port sets the SW_SMI_STS bit. Note
that if the SW_SMI_EN bit is set (see bit-6 of the
Global Enable register at offset 2Ah), then an SMI is
generated.
Power Management I/O-Space Registers
VT82C686B