VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Page 105/128:

System Management Bus I/O-Space Registers

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System Management Bus I/O-Space Registers

The base address for these registers is defined in Rx93-90 of
the Function 4 PCI configuration registers.
Management Bus I/O space is enabled for access by the system
if RxD2[0] = 1.
I/O Offset 00 – SMBus Host Status............................... RWC
7-5
Reserved
........................................ always reads 0
4
Failed Bus Transaction....................................RWC
0
SMBus interrupt not caused by failed bus
transaction ..............................................default
1
SMBus interrupt caused by failed bus
transaction.
This bit may be set when the
KILL bit (I/O Rx02[1]) is set and can be
cleared by writing a 1 to this bit position.
3
Bus Collision.....................................................RWC
0
SMBus interrupt not caused by transaction
collision..................................................default
1
SMBus
interrupt
collision. This bit is only set by hardware and
can be cleared by writing a 1 to this bit
position.
2
Device Error .....................................................RWC
0
SMBus interrupt not caused by generation of
an SMBus transaction error....................default
1
SMBus interrupt caused by generation of an
SMBus transaction error (illegal command
field, unclaimed host-initiated cycle, or host
device timeout).
hardware and can be cleared by writing a 1 to
this bit position.
1
SMBus Interrupt..............................................RWC
0
SMBus interrupt not caused by host command
completion..............................................default
1
SMBus interrupt caused by host command
completion. This bit is only set by hardware
and can be cleared by writing a 1 to this bit
position.
0
Host Busy
..........................................................RO
0
SMBus controller host interface is not
processing a command ...........................default
1
SMBus host controller is busy processing a
command. None of the other SMBus registers
should be accessed if this bit is set.
Revision 1.71 June 9, 2000
The System
I/O Offset 01h – SMBus Slave Status ........................... RWC
7-6
5
4
caused
by
transaction
3
This bit is only set by
2
1
0
-99-
Reserved
........................................always reads 0
Alert Status ..................................................... RWC
0
SMBus interrupt not caused by SMBALERT#
signal .................................................... default
1
SMBus interrupt caused by SMBALERT#
signal. This bit will be set only if the Alert
Enable bit is set in the SMBus Slave Control
Register at I/O Offset R08[3]. This bit is only
set by hardware and can be cleared by writing
a 1 to this bit position.
Shadow 2 Status............................................... RWC
0
SMBus interrupt not caused by address match
to SMBus Shadow Address Port 2......... default
1
SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 2.
This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
Shadow 1 Status............................................... RWC
0
SMBus interrupt not caused by address match
to SMBus Shadow Address Port 1......... default
1
SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 1.
This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
Slave Status ..................................................... RWC
0
SMBus interrupt not caused by slave event
match .................................................... default
1
SMBus interrupt or resume event caused by
slave cycle event match of the SMBus Slave
Command Register at PCI Function 4
Configuration Offset D3h (command match)
and the SMBus Slave Event Register at
SMBus Base + Offset 0Ah (data event match).
This bit is only set by hardware and can be
cleared by writing a 1 to this bit position.
Reserved
........................................always reads 0
Slave Busy ......................................................... RO
0
SMBus controller slave interface is not
processing data ...................................... default
1
SMBus controller slave interface is busy
receiving data.
None of the other SMBus
registers should be accessed if this bit is set.

System Management Bus I/O-Space Registers

VT82C686B