VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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Page 16/128:

CPU Interface

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Signal Name
CPURST
INTR
NMI
INIT
STPCLK#
SMI#
FERR#
IGNNE#
SLP# / GPO7
A20M#
Note: Connect each of the above signals to 4.7K
Advanced Programmable Interrupt Controller (APIC)
Signal Name
WSC# / GPI3 / LID
APICD0 / GPO1 / SUSA#
APICD1 / SUSCLK
For programming information, refer to Function 0 Rx74,77, Function 4 Rx54[3-2], and Memory Mapped / Indexed APIC registers.
Rx77[4] is “Internal APIC Enable”.
The clock source used by the chip to clock the internal I/O APIC is OSC (14.31818 MHz), so OSC must be externally connected to
the CPU I/O APIC clock input.
Revision 1.71 June 9, 2000

CPU Interface

Pin #
I/O
Signal Description
V8
OD
CPU Reset. The VT82C686B asserts CPURST to reset the CPU during
power-up.
W8
OD
CPU Interrupt. INTR is driven by the VT82C686B to signal the CPU
that an interrupt request is pending and needs service.
U7
OD
Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt
to the CPU. The VT82C686B generates an NMI when either SERR# or
IOCHK# is asserted.
T6
OD
Initialization. The VT82C686B asserts INIT if it detects a shut-down
special cycle on the PCI bus or if a soft reset is initiated by the register
W7
OD
Stop Clock. STPCLK# is asserted by the VT82C686B to the CPU to
throttle the processor clock.
U6
OD
System Management Interrupt. SMI# is asserted by the VT82C686B to
the CPU in response to different Power-Management events.
V7
I
Numerical Coprocessor Error. This signal is tied to the coprocessor
error signal on the CPU. Internally generates interrupt 13 if active.
Y8
OD
Ignore Numeric Error. This pin is connected to the “ignore error” pin on
the CPU.
T7
OD
Sleep (Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1
CPUs only. Not currently used with socket-7 CPUs.
Y7
OD
A20 Mask. Connect to A20 mask input of the CPU to control address bit-
20 generation. Logical combination of the A20GATE input (from internal
or external keyboard controller) and Port 92 bit-1 (Fast_A20).
pullup resistors to VCC3.
Pin #
I/O
Signal Description
U10
I
Write Snoop Complete. Asserted by the north bridge to indicate that all
snoop activity on the CPU bus initiated by the last PCI-to-DRAM write
is complete and that it is safe to perform an APIC interrupt.
V9
IO
APIC Data 0.
T10
IO
APIC Data 1.
-10-
VT82C686B
Pinouts