VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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CMOS / RTC Registers
Port 70 - CMOS Address .................................................. RW
7
NMI Disable......................................................... RW
0
Enable NMI Generation. NMI is asserted on
encountering IOCHCK# on the ISA bus or
SERR# on the PCI bus.
1
Disable NMI Generation ........................default
CMOS Address (lower 128 bytes)....................... RW
6-0
Port 71 - CMOS Data........................................................ RW
CMOS Data (128 bytes)
7-0
Note:
Ports 70-71 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 70-71 will be directed to an
external RTC.
Port 72 - CMOS Address .................................................. RW
CMOS Address (256 bytes)................................. RW
7-0
Port 73 - CMOS Data........................................................ RW
CMOS Data (256 bytes)
7-0
Note:
Ports 72-73 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 72-73 will be directed to an
external RTC.
Port 74 - CMOS Address .................................................. RW
CMOS Address (256 bytes)................................. RW
7-0
Port 75 - CMOS Data........................................................ RW
7-0
CMOS Data (256 bytes)
Note:
Ports 74-75 may be accessed only if Function 0 Rx5B
bit-1 is set to one to enable the internal RTC SRAM
and if Rx48 bit-3 (Port 74/75 Access Enable) is set to
one to enable port 74/75 access.
Note:
Ports 70-71 are compatible with PC industry-
standards and may be used to access the lower 128
bytes of the 256-byte on-chip CMOS RAM. Ports
72-73 may be used to access the full extended 256-
byte space. Ports 74-75 may be used to access the
full on-chip extended 256-byte space in cases where
the on-chip RTC is disabled.
Note:
The system Real Time Clock (RTC) is part of the
“CMOS” block.
The RTC
located at specific offsets in the CMOS data area (0-
0Dh and 7D-7Fh). Detailed descriptions of CMOS /
RTC operation and programming can be obtained
from the VIA VT82887 Data Book or numerous
other industry publications.
definition of the RTC register locations and bits are
summarized in the following table:
Revision 1.71 June 9, 2000
Offset Description
00
Seconds
01
Seconds Alarm
02
Minutes
03
Minutes Alarm
04
Hours
05
Hours Alarm
06
Day of the Week Sun=1: 01-07h
07
Day of the Month
08
Month
09
Year
0A
Register A
0B
Register B
0C
Register C
0D
Register D
0E-7C Software-Defined Storage Registers (111 Bytes)
Offset Extended Functions
7D
Date Alarm
control registers are
7E
Month Alarm
7F
Century Field
80-FF Software-Defined Storage Registers (128 Bytes)
For reference, the
Table 5. CMOS Register Summary
-44-
Binary Range BCD Range
00-3Bh
00-3Bh
00-3Bh
00-3Bh
am 12hr: 01-1Ch
pm 12hr: 81-8Ch
24hr: 00-17h
am 12hr: 01-1Ch
pm 12hr: 81-8Ch
24hr: 00-17h
01-1Fh
01-0Ch
00-63h
Update In Progress
7
UIP
DV2-0 Divide (010=ena osc & keep time)
6-4
3-0
RS3-0 Rate Select for Periodic Interrupt
7
SET
Inhibit Update Transfers
6
PIE
Periodic Interrupt Enable
5
AIE
Alarm Interrupt Enable
4
UIE
Update Ended Interrupt Enable
3
SQWE No function (read/write bit)
2
DM
Data Mode (0=BCD, 1=binary)
1
24/12
Hours Byte Format (0=12, 1=24)
0
DSE
Daylight Savings Enable
7
IRQF Interrupt Request Flag
6
PF
Periodic Interrupt Flag
5
AF
Alarm Interrupt Flag
4
UF
Update Ended Flag
3-0
0
Unused (always read 0)
7
VRT
Reads 1 if VBAT voltage is OK
6-0
0
Unused (always read 0)
Binary Range BCD Range
01-1Fh
01-0Ch
13-14h
Register Descriptions - Legacy I/O Ports
VT82C686B
00-59h
00-59h
00-59h
00-59h
01-12h
81-92h
00-23h
01-12h
81-92h
00-23h
01-07h
01-31h
01-12h
00-99h
01-31h
01-12h
19-20h