VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 87/128

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF
Function 4 Regs - Power Management, SMBus and HWM
This section describes the ACPI (Advanced Configuration and
Power
Interface)
Power
Management
VT82C686B which includes a System Management Bus
(SMBus) interface controller and Hardware Monitoring
(HWM) subsystem. The power management system of the
VT82C686B supports both ACPI and legacy power
management functions and is compatible with the APM v1.2
and ACPI v1.0 specifications.
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
Vendor ID ................. (1106h = VIA Technologies)
0-7
Offset 3-2 - Device ID ......................................................... RO
0-7
Device ID
................ (3057h = ACPI Power Mgmt)
Offset 5-4 - Command ....................................................... RW
15-8 Reserved
........................................ always reads 0
7
Address Stepping ........................................fixed at 0
6
Reserved (parity error response) ..................fixed at 0
5
Reserved (VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate ...................fixed at 0
3
Reserved (special cycle monitoring) ............fixed at 0
2
Bus Master .................................................fixed at 0
1
Memory Space.............................................fixed at 0
0
I/O Space
.................................................fixed at 0
Offset 7-6 - Status ........................................................... RWC
15
Detected Parity Error ........................ always reads 0
14
Signalled System Error...................... always reads 0
13
Received Master Abort...................... always reads 0
12
Received Target Abort ...................... always reads 0
11
Signalled Target Abort ...................... always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .....................................default (fixed)
10 Slow
11 Reserved
8
Data Parity Detected.......................... always reads 0
7
Fast Back to Back Capable ............... always reads 1
6-0
Reserved
........................................ always reads 0
Revision 1.71 June 9, 2000
system of
the
Offset 8 - Revision ID (nnh) .............................................. RO
7-0
Silicon Revision Code
Offset 9 - Programming Interface (00h) .......................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 61h.
Offset A - Sub Class Code (00h) ....................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 62h.
Offset B - Base Class Code (00h) ...................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 63h.
Offset 0D - Latency Timer ............................................... RW
Timer Value ..............................................default = 0
7-0
Offset 0E - Header Type (00h) .......................................... RO
-81-
Function 4 Regs - Power Management, SMBus and HWM
VT82C686B