21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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21150
15.1.26
I/O Limit Address Upper 16 Bits Register—Offset 32h
This section describes the I/O limit address upper 16 bits register.
This register must be initialized by configuration software.
Dword address = 30h
Byte enable p_cbe_l<3:0> = 00xxb
Dword Bit
I/O limit address upper 16
31:16
bits <31:16>
15.1.27
Subsystem Vendor ID Register—Offset 34h
This section describes the subsystem vendor ID register.
Dword address = 34h
Byte enable p_cbe_l<3:0> = xx00b
Dword Bit
15:0
Subsystem vendor ID
15.1.28
ECP Pointer Register—Offset 34h
This section describes the ECP pointer register.
Dword address = 34h
Byte enable p_cbe_l<3:0> = 0000b
Dword Bit
7:0
ECP_PTR
31:8
Reserved
118
Name
R/W
Defines the upper 16 bits of a 32-bit top
address of an address range used by the
21150 to determine when to forward I/O
transactions from one interface to the other.
R/W
The I/O address range adheres to 4KB
alignment and granularity.
Reset value: 0.
Name
R/W
Provides a mechanism allowing add-in cards to
distinguish their cards from one another. The
21150 provides a writable subsystem vendor
R/W
ID that can be initialized during POST. This
register is only implemented in the 21150-AA.
Reset to 0.
Name
R/W
Enhanced Capabilities Port (ECP) offset
pointer. Reads as DCh in the 21150-AB and
later revisions to indicate that the first item,
R
which corresponds to the power management
registers, resides at that configuration offset.
This is a R/W register with no side effects in
the 21150-AA.
Reserved. The 21150-AB and later revisions
R
return 0 when read. This is a R/W register with
no side effects in the 21150-AA.
Description
Description
Description
Preliminary
Datasheet

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