21150-AB Intel Corporation, 21150-AB Datasheet - Page 68

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
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21150
5.3.2
60
Figure 17. Memory Transaction Forwarding Using Base and Limit Registers
Prefetchable Memory Base and Limit Address Registers
Locations accessed in the prefetchable memory address range must have true memory-like
behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable
memory location must have no side effects. The 21150 prefetches for all types of memory read
commands in this address space.
The prefetchable memory base address and prefetchable memory limit address registers define an
address range that the 21150 uses to determine when to forward memory commands. The 21150
forwards a memory transaction from the primary to the secondary interface if the transaction
address falls within the prefetchable memory address range. The 21150 ignores memory
transactions initiated on the secondary interface that fall into this address range. The 21150 does
not respond to any transactions that fall outside this address range on the primary interface and
forwards those transactions upstream from the secondary interface (provided that they do not fall
into the memory-mapped I/O range or are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional registers to
define the upper 32 bits of the memory address range, the prefetchable memory base address upper
32 bits register, and the prefetchable memory limit address upper 32 bits register. For address
comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like
a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit
value of 0 is compared to the prefetchable memory base address upper 32 bits register and the
prefetchable memory limit address upper 32 bits register. The prefetchable memory base address
upper 32 bits register must be 0 in order to pass any single address cycle transactions downstream.
Section 5.3.3
further describes 64-bit addressing support.
Primary
Interface
Note:
DAC
SAC
SAC
DAC
SAC
SAC
DAC – Dual Address Cycle
SAC – Single Address Cycle
Prefetchable Memory Limit
Prefetchable Memory Base
Memory-Mapped I/O Limit
Memory-Mapped I/O Base
Memory Address Space
1MB
Multiple
1MB
Multiple
Secondary
Interface
DAC
4GB
SAC
SAC
LJ-04639.AI4
DAC
SAC
SAC
Preliminary
Datasheet

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