21150-AB Intel Corporation, 21150-AB Datasheet - Page 81

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
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7.2.4
Preliminary
Datasheet
For upstream transactions, in the case where the parity error is being passed back from the target
bus and the initiator bus, the following events occur:
Posted Write Transactions
During downstream posted write transactions, when the 21150, responding as a target, detects a
data parity error on the initiator (primary) bus, the following events occur:
Similarly, during upstream posted write transactions, when the 21150, responding as a target,
detects a data parity error on the initiator (secondary) bus, the following events occur:
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of s_perr_l, the following events occur:
During upstream write transactions, when a data parity error is reported on the target (primary) bus
by the target’s assertion of p_perr_l, the following events occur:
The 21150 asserts s_perr_l two cycles after the data transfer, if both of the following are true:
The 21150 completes the transaction normally.
The 21150 asserts p_perr_l two cycles after the data transfer, if the primary interface parity
error response bit is set in the command register.
The 21150 sets the primary interface parity error detected bit in the status register.
The 21150 captures and forwards the bad parity condition to the secondary bus.
The 21150 completes the transaction normally.
The 21150 asserts s_perr_l two cycles after the data transfer, if the secondary interface parity
error response bit is set in the bridge control register.
The 21150 sets the secondary interface parity error detected bit in the secondary status register.
The 21150 captures and forwards the bad parity condition to the primary bus.
The 21150 completes the transaction normally.
The 21150 sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of
the following conditions are met:
The 21150 sets the data parity detected bit in the status register, if the primary interface parity
error response bit is set in the command register.
— The primary interface parity error response bit is set in the command register.
— The secondary interface parity error response bit is set in the bridge control register.
— The SERR# enable bit is set in the command register.
— The device-specific p_serr_l disable bit for posted write parity errors is not set.
— The secondary interface parity error response bit is set in the bridge control register.
— The primary interface parity error response bit is set in the command register.
— The 21150 did not detect the parity error on the primary (initiator) bus; that is, the parity
error was not forwarded from the primary bus.
21150
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