21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

CaseQFP  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 81/164

Download datasheet (812Kb)Embed
PrevNext
For upstream transactions, in the case where the parity error is being passed back from the target
bus and the initiator bus, the following events occur:
The 21150 asserts s_perr_l two cycles after the data transfer, if both of the following are true:
— The primary interface parity error response bit is set in the command register.
— The secondary interface parity error response bit is set in the bridge control register.
The 21150 completes the transaction normally.
7.2.4
Posted Write Transactions
During downstream posted write transactions, when the 21150, responding as a target, detects a
data parity error on the initiator (primary) bus, the following events occur:
The 21150 asserts p_perr_l two cycles after the data transfer, if the primary interface parity
error response bit is set in the command register.
The 21150 sets the primary interface parity error detected bit in the status register.
The 21150 captures and forwards the bad parity condition to the secondary bus.
The 21150 completes the transaction normally.
Similarly, during upstream posted write transactions, when the 21150, responding as a target,
detects a data parity error on the initiator (secondary) bus, the following events occur:
The 21150 asserts s_perr_l two cycles after the data transfer, if the secondary interface parity
error response bit is set in the bridge control register.
The 21150 sets the secondary interface parity error detected bit in the secondary status register.
The 21150 captures and forwards the bad parity condition to the primary bus.
The 21150 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of s_perr_l, the following events occur:
The 21150 sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of
the following conditions are met:
— The SERR# enable bit is set in the command register.
— The device-specific p_serr_l disable bit for posted write parity errors is not set.
— The secondary interface parity error response bit is set in the bridge control register.
— The primary interface parity error response bit is set in the command register.
— The 21150 did not detect the parity error on the primary (initiator) bus; that is, the parity
error was not forwarded from the primary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus
by the target’s assertion of p_perr_l, the following events occur:
The 21150 sets the data parity detected bit in the status register, if the primary interface parity
error response bit is set in the command register.
Preliminary
Datasheet
21150
73