RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 20/74:

Power Supply Requirements

Download datasheet (664Kb)Embed
PrevNext
®
®
LV Intel
Pentium
III Processor 512K
3.5
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, Intel recommends that the LV Intel Pentium
512K and the other 1.5 V JTAG specification compliant devices be placed last in the JTAG chain,
behind any system devices with 3.3 V or 5.0 V JTAG interfaces. A translation buffer should be
used to reduce the TDO output voltage of the last 3.3/5.0 V device down to the 1.5 V range that the
processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage
level.
A Debug Port and connector may be placed at the start and at the end of the JTAG chain that
contains the processor, with TDI to the first component coming from the Debug Port, and TDO
from the last component going to the Debug Port. There are no requirements for placing the
processor in the JTAG chain, except for those that are dictated by the voltage requirements of the
TAP signals.
3.6

Power Supply Requirements

3.6.1
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. These fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot).
3.6.2
Processor V
CC
The regulator for the V
Table
7) while maintaining the required tolerances (defined in
specifications can result in timing violations (during V
component (during V
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL bus operation. The minimum recommendation for the processor decoupling
requirement is listed below.
The LV Intel Pentium
Six 0.68- F capacitors are on V
package capacitors, sufficient board level capacitors are also necessary for power supply
decoupling. These guidelines are as follows:
High and Mid Frequency V
directly under the package on the solder side of the motherboard, using at least two vias per
capacitor node. Ten 10-µF X7R 6.3 V 1206-size ceramic capacitors should be placed around
the package periphery near the balls. Trace lengths to the vias should be designed to minimize
inductance. Avoid bending traces to minimize ESL.
High and Mid Frequency V
to the package. Via and trace guidelines are the same as above.
20
Table
Decoupling
CORE
input must be capable of delivering the dI
CC CORE
CC CORE
overshoot).
CC CORE
processor 512K has eight 0.68-µF surface mount decoupling capacitors.
III
and two 0.68-µF capacitors are on V
CC CORE
decoupling – Place twenty-four 0.22-µF 0603 capacitors
CC CORE
decoupling – Place ten 1-µF X7R 0603 ceramic capacitors close
TT
processor
III
7. Failure to do so can result in timing
/dt (defined in
CC CORE
Table
9). Failure to meet these
sag) or a reduced lifetime of the
. In addition to the
TT
Datasheet