PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 115/202:

POWER-ON RESET

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11.2.1

POWER-ON RESET

The on-chip POR circuit holds the chip in Reset until
V
has reached a high enough level for proper
DD
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to V
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
V
is required. See Section 14.0 “Electrical Specifi-
DD
cations” for details. If the BOR is enabled, the maxi-
mum rise time specification does not apply. The BOR
circuitry will keep the device in Reset until V
V
(see
Section 11.2.4
“Brown-Out
BOD
(BOR)”).
Note:
The POR circuit does not produce an
internal Reset when V
DD
re-enable the POR, V
must reach Vss
DD
for a minimum of 100 μs.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
11.2.2
MCLR
PIC16F688 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
. The use of an RC
DD
network, as shown in Figure 11-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to V
© 2007 Microchip Technology Inc.
FIGURE 11-2:
V
DD
. This
DD
R1
1 kΩ (or greater)
C1
reaches
0.1 μF
DD
(optional, not critical)
Reset
declines. To
11.2.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
DD
uration bit, PWRTE, can disable (if set) or enable (if
cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• V
variation
DD
• Temperature variation
• Process variation
See
DC
parameters
“Electrical Specifications”).
Note:
Voltage spikes below V
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to V
.
DD
PIC16F688
RECOMMENDED
MCLR
CIRCUIT
PIC16F688
MCLR
to rise to an acceptable level. A Config-
for
details
(Section 14.0
at the MCLR
SS
Ω
should be used when
.
SS
DS41203D-page 113