PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 121/202:

When an instruction that clears the GIE

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11.3
Interrupts
The PIC16F688 has multiple sources of interrupt:
• External Interrupt RA2/INT
• TMR0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• EUSART Receive and Transmit interrupts
The Interrupt Control (INTCON) register and Peripheral
Interrupt Request 1 (PIR1) register record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE bit of the INTCON
register, enables (if set) all unmasked interrupts, or dis-
ables (if cleared) all interrupts. Individual interrupts can
be disabled through their corresponding enable bits in
the INTCON register and PIE1 register. GIE is cleared
on Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• EUSART Receive and Transmit Interrupts
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
© 2007 Microchip Technology Inc.
PIC16F688
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 11-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless
of
the
status
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
For additional information on Timer1, A/D or data
EEPROM modules, refer to the respective peripheral
section.
DS41203D-page 119
of
their