PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 122/228:

A/D Operation During Sleep

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PIC16F87/88
12.6

A/D Operation During Sleep

The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES registers. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction
immediately
instruction that sets the GO/DONE bit.
TABLE 12-2:
REGISTERS/BITS ASSOCIATED WITH A/D
Address
Name
Bit 7
Bit 6
0Bh, 8Bh
INTCON
GIE
PEIE
10Bh,
18Bh
(1)
0Ch
PIR1
ADIF
(1)
8Ch
PIE1
ADIE
(2)
1Eh
ADRESH
A/D Result Register High Byte
(2)
9Eh
ADRESL
A/D Result Register Low Byte
(2)
1Fh
ADCON0
ADCS1 ADCS0
(2)
9Fh
ADCON1
ADFM
ADCS2
(2
9Bh
ANSEL
ANS6
05h
PORTA
RA7
RA6
(PIC16F87)
(PIC16F88)
05h, 106h PORTB
RB7
RB6
(PIC16F87)
(PIC16F88)
85h
TRISA
TRISA7 TRISA6 TRISA5
86h, 186h TRISB
TRISB7 TRISB6
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
2:
PIC16F88 only.
3:
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
DS30487C-page 120
12.7
Effects of a Reset
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is
not
modified
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
12.8
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 counter will be reset to zero. Timer1 is reset
to automatically repeat the A/D acquisition period with
minimal
software
ADRESH:ADRESL to the desired location). The appro-
priate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
follows
the
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 counter.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF -000 0000 -000 0000
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE -000 0000 -000 0000
CHS2
CHS1
CHS0 GO/DONE
VCFG1
VCFG0
ANS5
ANS4
ANS3
ANS2
ANS1
RA5
RA4
RA3
RA2
RB5
RB4
RB3
RB2
(3)
PORTA Data Direction Register (TRISA<4:0>)
TRISB5 TRISB4 TRISB3
TRISB2
TRISB1 TRISB0
for
a
Power-on
Reset.
The
overhead
(moving
the
Value on
Value on
Bit 0
all other
POR, BOR
Resets
RBIF
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
ADON
0000 00-0 0000 00-0
0000 ---- 0000 ----
ANS0
-111 1111 -111 1111
RA1
RA0
xxxx 0000
uuuu 0000
xxx0 0000
uuu0 0000
RB1
RB0
xxxx xxxx
uuuu uuuu
00xx xxxx
00uu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
 2005 Microchip Technology Inc.