NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 

Specifications of NH82801GBM SL8YB

CaseBGADate_code07+
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Note that there is no STOP condition before the repeated START condition, and that a
NACK signifies the end of the read transfer.
Note:
E32B bit in the Auxiliary Control register must be set when using this protocol.
See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
5.21.2
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The ICH7 continuously monitors the
SMBDATA line. When the ICH7 is attempting to drive the bus to a 1 by letting go of the
SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus
and the ICH7 will stop transferring data.
If the ICH7 sees that it has lost arbitration, the condition is called a collision. The ICH7
will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an
interrupt or SMI#. The processor is responsible for restarting the transaction.
When the ICH7 is a SMBus master, it drives the clock. When the ICH7 is sending
address or command as an SMBus master, or data bytes as a master on writes, it drives
data relative to the clock it is also driving. It will not start toggling the clock until the
start or stop condition meets proper setup and hold time. The ICH7 will also provide
minimum time between SMBus transactions as a master.
Note:
The ICH7 supports the same arbitration protocol for both the SMBus and the System
Management (SMLINK) interfaces.
5.21.3
Bus Timing
5.21.3.1
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH7
as an SMBus master would like. They have the capability of stretching the low time of
the clock. When the ICH7 attempts to release the clock (allowing the clock to go high),
the clock will remain low for an extended period of time.
The ICH7 monitors the SMBus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
5.21.3.2
Bus Time Out (Intel
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The ICH7 will discard the cycle and set the DEV_ERR bit. The time out
minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH7 will start
after the last bit of data is transferred by the ICH7 and it is waiting for a response.
The 25 ms timeout counter will not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that
the system has not locked up).
224
®
ICH7 as SMBus Master)
Functional Description
®
Intel
ICH7 Family Datasheet