NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 

Specifications of NH82801GBM SL8YB

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Download datasheet (7Mb)Embed
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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.3
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address: 04h
Default Value:
0000h
Bit
15:11
Reserved
Interrupt Disable — R/W.
10
0 = Enable.
1 = Disables LAN controller to assert its INTA signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller
9
will not run fast back-to-back PCI cycles.
SERR# Enable (SERR_EN) — R/W.
8
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.
Parity Error Response (PER) — R/W.
0 = The LAN controller will ignore PCI parity errors.
6
1 = The integrated LAN controller will take normal action when a PCI parity error is
detected and will enable generation of parity on DMI.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.
Memory Write and Invalidate Enable (MWIE) — R/W.
4
0 = Disable. The LAN controller will not use the Memory Write and Invalidate command.
1 = Enable.
Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special
3
cycles.
Bus Master Enable (BME) — R/W.
0 = Disable.
2
1 = Enable. The Intel
master.
Memory Space Enable (MSE) — R/W.
0 = Disable.
1
1 = Enable. The ICH7’s integrated LAN controller will respond to the memory space
accesses.
I/O Space Enable (IOSE) — R/W.
0 = Disable.
0
1 = Enable. The ICH7’s integrated LAN controller will respond to the I/O space
accesses.
®
Intel
ICH7 Family Datasheet
05h
Attribute:
–
Size:
Description
®
ICH7’s integrated LAN controller may function as a PCI bus
RO, R/W
16 bits
305

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