NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 

Specifications of NH82801GBM SL8YB

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LPC Interface Bridge Registers (D31:F0)
10.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h
Default Value:
0007h
Lockable:
No
Bit
15:10
Reserved
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
6
1 = Enables the Intel
backbone interface.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
3
Special Cycle Enable (SCE) — RO. Hardwired to 0.
2
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
1
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
0
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
10.1.4
PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06
Default Value:
0210h
Lockable:
Noh
Note:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity
error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is
0.
15
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system
14
error to the internal SERR# logic.
Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
13
1 = The bridge received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
12
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
®
Intel
ICH7 Family Datasheet
05h
Attribute:
–
Size:
Power Well:
Description
®
ICH7 LPC bridge to respond to parity errors detected on
07h
Attribute:
–
Size:
Power Well:
Description
R/W, RO
16-bit
Core
RO, R/WC
16-bit
Core
365

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