NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 525

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
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SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Intel
®
ICH7 Family Datasheet
(Desktop
(Mobile)
23:20
23:20
Only)
12:8
Only
7:5
4:0
Bit
25
24
19
18
17
16
15
14
13
Supports Activity LED (SAL) — RO. Indicates that the SATA controller supports
a single output pin (SATALED#) which indicates activity.
Supports Command List Override (SCLO) — R/WO. When set to 1, indicates that
the HBA supports the PxCMD.CLO bit and it's associated function. When cleared to
'0', The HBA is not capable of clearing the BSY and DRQ bits in the Status register
in order to issue a software reset if these bits are still set from a previous
operation.
Interface Speed Support (ISS) — R/WO. Indicates the maximum speed the
SATA controller can support on its ports.
2h =3.0 Gb/s.
Interface Speed Support (ISS) — RO. Indicates the maximum speed the SATA
controller can support on its ports.
1h =1.5 Gb/s.
Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI
Revision 1.0 specification
Supports Port Selector Acceleration — RO. Port Selectors not supported.
Supports Port Multiplier (PMS) — R/WO. ICH7 does not support port multiplier.
BIOS/SW shall write this bit to ‘0’ during AHCI initialization.
Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the
AHCI Revision 1.0 specification.
NOTE: Port Multiplier not supported by ICH7.
PIO Multiple DRQ Block (PMD) — R/WO. The SATA controller supports PIO
Multiple DRQ Command Block
Slumber State Capable (SSC) — RO. The SATA controller supports the slumber
state.
Partial State Capable (PSC) — RO. The SATA controller supports the partial state.
Number of Command Slots (NCS) — RO. Hardwired to 1Fh to indicate support for
32 slots.
Reserved. Returns 0.
Number of Ports (NPS) — RO. Hardwired to 3h to indicate support for 4 ports. Note
that the number of ports indicated in this field may be more than the number of
ports indicated in the PI (ABAR + 0Ch) register.
Description
525

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