EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
Page 29/42

Download datasheet (729Kb)Embed
PrevNext
Table 20. EP910 Internal Timing Parameters
Symbol
Parameter
t
Input pad and buffer delay
IN
t
I/O input pad and buffer delay
IO
t
Logic array delay
LAD
t
Output buffer and pad delay
OD
t
Output buffer enable delay
ZX
t
Output buffer disable delay
XZ
t
Register setup time
SU
t
Register hold time
H
t
Array clock delay
IC
t
Global clock delay
ICS
t
Feedback delay
FD
t
Register clear time
CLR
Notes to tables:
(1)
These values are specified in
(2)
See
Application Note 78 (Understanding MAX 5000 & Classic Timing)
timing parameters.
(3)
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4)
Sample-tested only for an output change of 500 mV.
(5)
The f
values represent the highest frequency for pipelined data.
MAX
(6)
Measured with a device programmed as a 24-bit counter.
(7)
Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Altera Corporation
Condition
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
Table 15 on page
770.
Classic EPLD Family Data Sheet
EP910-30
EP910-35
EP910-40
Min
Max
Min
Max
Min
9.0
10.0
3.0
3.0
14.0
16.0
7.0
9.0
7.0
9.0
7.0
9.0
12.0
13.0
15.0
12.0
12.0
12.0
17.0
19.0
2.0
2.0
4.0
6.0
17.0
19.0
in this data book for more information on Classic
Unit
Max
13.0
ns
3.0
ns
17.0
ns
10.0
ns
10.0
ns
10.0
ns
ns
ns
20.0
ns
1.0
ns
8.0
ns
20.0
ns
773