M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


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Chapter 5
Interrupt
5.1.3 Hardware Interrupts
There are Two types in hardware Interrupts; special interrupts and Peripherai I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
• Reset
____________
A reset occurs when the RESET pin is pulled low.
______
• NMI interrupt
This interrupt occurs when the NMI pin is pulled low.
________
• DBC interrupt
This interrupt is used exclusively for debugger purposes. You normally do not need to use this interrupt.
• Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
• Single-step interrupt
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated
each time an instruction is executed.
• Address-match interrupt
This interrupt occurs when the program's execution address matches the content of the address match
register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
(2) Peripheral I/O interrupts
These interrupts are generated by the peripheral functions built into the microcomputer system. The
types of built-in peripheral functions vary with each M16C model, so do the types of interrupt causes. The
interrupt vector table uses the same software interrupt numbers 0–31 that are used by the INT instruction.
Peripheral I/O interrupts are maskable interrupts. For details about peripheral I/O interrupts, refer to the
M16C User’s Manual.
______
250
5.1 Outline of Interrupt