M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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Chapter 2 Addressing Modes
2.4 Special Instruction Addressing
20-bit absolute
The value indicated by abs20 constitutes
abs20
the effective address to be operated on.
The effective address range is 00000
FFFFF
.
16
This addressing can be used in LDE, STE,
JSR, and JMP instructions.
Address register relative with
20-bit displacement
The address indicated by displacement
dsp:20[A0]
(dsp) plus the content of address register
dsp:20[A1]
(A0/A1)—added not including the sign
bits—constitutes the effective address to
be operated on.
However, if the addition resulted in exceed-
ing FFFFF
, the bits above bit 21 are
16
ignored, and the address returns to
00000
.
16
This addressing can be used in LDE, STE,
JMPI, and JSRI instructions.
The following lists the addressing mode and
instruction combinations that can be used.
dsp:20[A0]
LDE, STE, JMPI, and JSRI in-
structions
dsp:20[A1]
JMPI and JSRI instructions
32-bit address register indirect
The address indicated by 32 concat-
[A1A0]
enated bits of address registers (A0
and A1) constitutes the effective
address to be operated on.
However, if the concatenated register
value exceeds FFFFF
above bit 21 are ignored.
This addressing can be used in LDE
and STE instructions.
to
16
abs20
LDE, STE instructions
Register
A0
address
JMPI, JSRI instructions
Register
address
A0 / A1
A1
b31
address-H
, the bits
16
27
2.4 Special Instruction Addressing
Memory
Memory
dsp
Memory
dsp
PC
Register
A0
b16 b15
b0
address-L
Memory
address