PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

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PIC16F684
12.4.2
TMR0 INTERRUPT
An overflow (FFh
00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
by
setting/clearing
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
TMR2IF
TMR2IE
TMR1IF
TMR1IE
C1IF
C1IE
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
CCP1IF
CCP1IE
DS41202C-page 102
12.4.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
T0IE
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
T0IF
T0IE
INTF
INTE
RAIF
RAIE
PEIE
GIE
Preliminary
 2004 Microchip Technology Inc.
Interrupt to CPU