PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

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PIC16F684
11.3
Enhanced PWM Mode
The Enhanced CCP module produces up to a 10-bit
resolution PWM output and may have up to four
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC. The pin
assignments are summarized in Table 11-3.
FIGURE 11-3:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
CCPR1H (Slave)
R
Comparator
(1)
TMR2
S
Comparator
Clear Timer2,
toggle PWM pin and
latch duty cycle
PR2
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to
create the 10-bit time base.
11.3.1
PWM OUTPUT CONFIGURATIONS
The P1M<1:0> bits in the CCP1CON register allows
one of four configurations:
• Single Output
• Half-bridge Output
• Full-bridge Output, Forward mode
• Full-bridge Output, Reverse mode
TABLE 11-3:
PIN ASSIGNMENTS FOR VARIOUS ENHANCED CCP MODES
ECCP Mode
Configuration
Compatible CCP
Dual PWM
Quad PWM
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1:
TRIS register values must be configured appropriately.
2:
With ECCP in Dual or Quad PWM mode, the C2OUT output control of PORTC must be disabled.
DS41202C-page 78
Figure 11-3 shows a simplified block diagram of PWM
operation.
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1M<1:0> and
CCP1M<3:0>
CCP1CON<3:0>,
TRISC bits must also be set as outputs.
P1M<1:0>
CCP1M<3:0>
2
4
CCP1/P1A
TRISC<5>
P1B
TRISC<4>
Output
Q
Controller
P1C
TRISC<3>
P1D
TRISC<2>
PWM1CON
The general relationship of the outputs in all
configurations is summarized in Figure 11-3.
Note:
Clearing the CCP1CON register will force
the PWM output latches to their default
inactive levels. This is not the PORTC I/O
data latch.
CCP1CON
RC5
RC4
CCP1
RC4/C2OUT
00xx11xx
P1A
P1B
10xx11xx
P1A
P1B
x1xx11xx
Preliminary
bits
(CCP1CON<7:6>
and
respectively).
The
appropriate
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/P1C
RC2/AN6/P1D
RC3
RC2
RC3/AN7
RC2/AN6
RC3/AN7
RC2/AN6
P1C
P1D
 2004 Microchip Technology Inc.