74ABT823 NXP [NXP Semiconductors], 74ABT823 Datasheet

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74ABT823

Manufacturer Part Number
74ABT823
Description
9-bit D-type flip-flop with reset and enable; 3-state
Manufacturer
NXP [NXP Semiconductors]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT823
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
74ABT823DB
Manufacturer:
NXP
Quantity:
3 451
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74ABT823D
74ABT823DB
74ABT823PW
Ordering information
Package
Temperature range Name
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
The 74ABT823 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master
reset input (MR) which are ideal for parity bus interfacing in systems using many
microprocessors.
The 74ABT823 is designed to eliminate the extra packages required to buffer existing
registers and provide extra data width for wider data and address paths of buses carrying
parity.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 03 — 23 March 2010
High-speed parallel registers with positive edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and −32 mA
Power-on 3-state
Power-on reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Product data sheet
Version
SOT137-1
SOT340-1
SOT355-1

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74ABT823 Summary of contents

Page 1

... The 74ABT823 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master reset input (MR) which are ideal for parity bus interfacing in systems using many microprocessors ...

Page 2

... D-type flip-flop with reset and enable; 3-state 001aaa847 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 1C2 ...

Page 3

... FF0 FF1 FF5 FF6 Q5 Q6 All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 FF2 FF3 FF4 ...

Page 4

... MR GND 12 13 001aal300 Pin All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 Description output enable input (active LOW) data input master reset input (active LOW) ...

Page 5

... Conditions output in OFF-state or HIGH-state V < < output in LOW-state All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 Output Operating mode Qn L clear H load and read data L NC hold Z high-impedance Min Max −0.5 +7.0 − ...

Page 6

... GND GND outputs HIGH-state outputs LOW-state outputs disabled All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 Min Typ Max 4 0.8 − −40 ...

Page 7

... ° 5.0 V −40 °C to +85 ° Min Typ Max 125 200 - 2.1 4.3 5.9 2.2 4.4 6.1 2.0 4.1 6.3 1.0 3.0 4.5 2.2 4.1 5.6 2.7 4.8 6.2 2.5 5.0 6.4 2.1 0.5 - +2.0 −0.5 - +2.0 2.1 0.2 - 3.3 1.5 - 1.3 0.0 - +1.0 −1.4 - +1.0 +1.3 −0.3 - +1.3 2.0 0.7 - 2.9 1.9 - 74ABT823 Min Max - 1 ± Unit = 5.0 V ± 0.5 V Min Max 125 - MHz 2.1 6.8 ns 2.2 6.7 ns 2.0 7.1 ns 1.0 5.3 ns 2.2 6.3 ns 2.7 6.9 ns 2.5 6 © NXP B.V. 2010. All rights reserved. ...

Page 8

... PHL GND GND t PHL All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 25 ° 5.0 V −40 °C to +85 ° 5.0 V ± 0 Min Typ Max Min 3.8 2.8 - 3.8 5.5 4.0 - 5.5 2.5 0.6 - 2.5 t PLH 001aac445 ...

Page 9

... GND GND t PZL 3 PZH GND All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 t su(L) t h(L) 001aac447 t PLZ + 0 PHZ − 0 001aac448 © NXP B.V. 2010. All rights reserved ...

Page 10

... 001aai298 8. Load ≤ 2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 DUT Test circuit of the pulse generator EXT PHL PLH PZH 500 Ω ...

Page 11

... 0.49 0.32 15.6 7.6 10.65 1.27 0.36 0.23 15.2 7.4 10.00 0.019 0.013 0.61 0.30 0.419 0.05 0.014 0.009 0.60 0.29 0.394 REFERENCES JEDEC JEITA MS-013 All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 θ detail 1.1 1.1 1.4 0.25 0.25 0.1 0.4 1.0 0.043 0.043 ...

Page 12

... 2.5 scale (1) ( 0.38 0.20 8.4 5.4 0.65 0.25 0.09 8.0 5.2 REFERENCES JEDEC JEITA MO-150 All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 detail 7.9 1.03 0.9 1.25 0.2 0.13 7.6 0.63 0.7 EUROPEAN PROJECTION ...

Page 13

... 2.5 scale (1) ( 0.30 0.2 7.9 4.5 0.65 0.19 0.1 7.7 4.3 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...

Page 14

... D-type flip-flop with reset and enable; 3-state Data sheet status Product data sheet Product specification Product specification All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 Change notice Supersedes - 74ABT823_2 Section 3 “Ordering information” and.Section - 74ABT823_1 - © NXP B.V. 2010. All rights reserved ...

Page 15

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 © NXP B.V. 2010. All rights reserved ...

Page 16

... For sales office addresses, please send an email to: 74ABT823_3 Product data sheet 9-bit D-type flip-flop with reset and enable; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 23 March 2010 74ABT823 © NXP B.V. 2010. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT823 All rights reserved. Date of release: 23 March 2010 Document identifier: 74ABT823_3 ...

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