74F673A Fairchild, 74F673A Datasheet

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74F673A

Manufacturer Part Number
74F673A
Description
16-Bit Serial-In / Serial/Parallel-Out Shift Register
Manufacturer
Fairchild
Datasheet
© 1999 Fairchild Semiconductor Corporation
74F673ASC
74F673APC
74F673ASPC
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a 3-
STATE serial output. In the Serial-Out mode, the data recir-
culates in the shift register. By means of a separate clock,
the contents of the shift register are transferred to the stor-
age register for parallel outputting. The contents of the stor-
age register can also be parallel loaded back into the shift
register. A HIGH signal on the Chip Select input prevents
both shifting and parallel transfer. The storage register may
be cleared via STMR.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
IEEE/IEC
M24B
N24C
N24A
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
DS009585
Features
Connection Diagram
Serial-to-parallel converter
16-bit serial I/O shift register
16-bit parallel-out storage register
Recirculating serial shifting
Recirculating parallel transfer
Common serial data I/O pin
Slim 24 lead package
Package Description
April 1988
Revised August 1999
www.fairchildsemi.com

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74F673A Summary of contents

Page 1

... Serial-In, Serial/Parallel-Out Shift Register General Description The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit Parallel-Out storage register. A single pin serves either as an input for serial entry STATE serial output. In the Serial-Out mode, the data recir- culates in the shift register ...

Page 2

... Active Parallel Load; No Shifting H HIGH Voltage Level L LOW Voltage Level  X Immaterial HIGH-to-LOW Transition www.fairchildsemi.com U.L. Description HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.0 150/40 50/33.3 parallel loading the shift register from the storage register, serial shifting is inhibited. The storage register has an asynchronous master reset (STMR) input that overrides all other inputs and forces the Q – ...

Page 3

... Block Diagram 3 www.fairchildsemi.com ...

Page 4

... Output HIGH Leakage Current CEX I Bus Drainage Test ZZ I Power Supply Current CCH I Power Supply Current CCL www.fairchildsemi.com Recommended Operating (Note 1) Conditions 150 125 C Free Air Ambient Temperature 150 C Supply Voltage 0.5V to 7.0V 0.5V to 7.0V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired ...

Page 5

... SI/O to SHCP 5. Min Typ Max Min 100 130 85 3.0 8.0 10.5 2.5 3.0 10.5 13.5 2.5 6.0 16.5 20.5 5.5 4.0 6.5 8.5 3.5 4.5 8.0 10.5 4.0 5.0 8.5 11.0 4.0 5.5 9.0 11.5 4.5 3.5 5.5 7.5 3.0 3.0 4.5 6.5 2.5 4.5 7.5 9.5 4.0 4.5 8.0 10.0 4.0 3.0 5.5 7.0 2.5 2.5 4.0 5.5 2 5. Min Max Min 3.5 4.0 6.0 7 3.0 3.5 3.0 3.5 3.0 3.5 3.0 3.5 5 www.fairchildsemi.com Units Max MHz 12.0 ns 15.0 22.5 ns 9.5 ns 12.0 12.5 13.0 ns 8.5 7.5 10.5 11.5 ns 8.0 6.5 Units Max ns ns ...

Page 6

... Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide www.fairchildsemi.com Package Number M24B Package Number N24A 6 ...

Page 7

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...

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