74F899 Fairchild, 74F899 Datasheet
74F899
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74F899 Summary of contents
Page 1
... Latchable Transceiver with Parity Generator/Checker General Description The 74F899 is a 9-bit to 9-bit parity transceiver with trans- parent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability the A-bus and the B-bus ...
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... ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A (B) communicates to Bus B (A), parity is gener- ated and passed on to the B (A) Bus as BPAR (APAR) ...
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... Generated parity also fed back through the B latch for generate/check as ERRB. H HIGH Voltage Level L LOW Voltage Level Note 1: O/E ODD/EVEN Functional Block Diagram Operation APAR/A0:7] Feed-through mode. Generated parity checked against APAR/A[0:7] BPAR/B[0:7] BPAR/B[0:7] X Immaterial 3 APAR. APAR. Generated APAR. BPAR. Generated parity BPAR. Generated BPAR. www.fairchildsemi.com ...
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... I Output Leakage OD Circuit Current I Input Low Current IL I Output Leakage Current IH I Current OZH www.fairchildsemi.com Recommended Operating (Note 2) Conditions 150 125 C Free Air Ambient Temperature 150 C Supply Voltage 0.5V to 7.0V 0. 5 Note 2: Absolute maximum ratings are values beyond which the device CC may be damaged or have its useful life impaired ...
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... Units Number Min Max 4.0 14.0 ns Figure 1 4.0 14.0 7.5 18.0 ns Figure 2 7.5 18.0 7.5 18.0 ns Figure 3 7.5 18.0 4.5 12.0 ns Figure 4 4.5 12.0 4.5 12.5 ns Figure 5 4.5 12.5 5.5 14.0 ns Figure 6 5.5 14.0 7.5 18.0 ns Figure 7 7.5 18.0 3.0 11.0 ns Figure 10 3.0 11.0 3.5 11.0 ns Figure 11 3.5 11.0 3.5 11.0 ns Figure 11 3.5 11.0 1.0 11.0 Figure 8, 1.0 11.0 ns Figure 9 1.0 8.0 Figure 8, 1.0 8.0 ns Figure 9 5.0 Figure 12, ns Figure 13 5.0 0 Figure 12, ns Figure 13 0 6.0 ns Figure 14 www.fairchildsemi.com ...
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... AC Path A , APAR B , BPAR BPAR A , APAR BPAR n (B APAR ERRA n (B ERRB) n www.fairchildsemi.com FIGURE 1. FIGURE 2. FIGURE 3. 6 ...
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... AC Path (Continued) O/E ERRA O/E ERRB O/E BPAR (O/E APAR) APAR ERRA (BPAR ERRB) FIGURE 4. FIGURE 5. FIGURE 6. 7 www.fairchildsemi.com ...
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... AC Path (Continued) ZH, HZ ZL, LZ www.fairchildsemi.com FIGURE 7. FIGURE 8. FIGURE 9. 8 ...
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... AC Path (Continued) SEL BPAR (SEL APAR) LEA BPAR, B[0:7] (LEB APAR, A[0:7]) TS(H), TH(H) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 10. FIGURE 11. FIGURE 12. 9 www.fairchildsemi.com ...
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... AC Path (Continued) TS(L), TH(L) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) www.fairchildsemi.com FIGURE 13. FIGURE 14. 10 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B 11 www.fairchildsemi.com ...
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... Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...