74VHCT573 Fairchild Semiconductor, 74VHCT573 Datasheet

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74VHCT573

Manufacturer Part Number
74VHCT573
Description
Octal D-Type Latch with 3-STATE Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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© 1999 Fairchild Semiconductor Corporation
74VHCT573AM
74VHCT573ASJ
74VHCT573AMTC
74VHCT573AN
74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a Latch Enable input (LE) and an Out-
put Enable input (OE). When the OE input is HIGH, the
eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
IEEE/IEC
MTC20
M20B
M20D
N20A
D
LE
OE
O
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
0
0
–D
–O
DS500028.prf
7
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
Features
Connection Diagram
High speed: t
High Noise Immunity: V
Power Down Protection is provided on all inputs and
outputs
Low Noise: V
Low Power Dissipation:
Pin and function compatible with 74HCT573
Description
I
CC
Package Description
4 A (max) @ T
PD
OLP
7.7 ns (typ) at T
1.6V (max)
IH
A
25 C
2.0V, V
January 1998
Revised April 1999
A
IL
25 C
www.fairchildsemi.com
0.8V

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74VHCT573 Summary of contents

Page 1

... MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT573AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Functional Description The VHCT573A contains eight D-type latches with 3- STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this con- n dition the latches are transparent, i.e., a ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT (Note 3) 0. (Note 4) Input Diode Current ( Output Diode Current (I ) (Note 5) ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation Delay Time PLH 5.0 0 PHL n t Propagation Delay Time PLH 5.0 0 PHL n t 3-STATE Output PZL ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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