AD7233 Analog Devices, AD7233 Datasheet
AD7233
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AD7233 Summary of contents
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... LDAC PRODUCT HIGHLIGHTS ® 1. Complete 12-Bit DACPORT . 2. The AD7233 is a complete, voltage output, 12-bit DAC on a single chip. This single-chip design is inherently more reli- able than multichip designs. 3. Simple 3-wire interface to most microcontrollers and DSP processors. 4. DAC Update Rate—300 kHz. ...
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... AD7233–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution 3 Relative Accuracy 3 Differential Nonlinearity 3 Bipolar Zero Error 3 Full-Scale Error 4 Full-Scale Temperature Coefficient DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance ANALOG OUTPUTS Output Voltage Range 4 DC Output Impedance ...
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... DIGITAL FEEDTHROUGH This is a measure of the voltage spike that appears on V result of feedthrough from the digital inputs on the AD7233 measured with LDAC held high. when the OUT ...
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... DAC latch under control of LDAC. Only the data in the DAC latch determines the analog output on the AD7233. A low SYNC input provides the frame synchronization signal which tells the AD7233 that valid serial data on the SDIN input V OUT will be available for the next 16 falling edges of SCLK. An inter- ...
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... RESET GATING –16 SIGNAL COUNTER/ DECODER GATED SCLK AUTO-UPDATE CIRCUITRY DB14 DB13 DB12 DB11 DON'T CARE DON'T CARE DON'T CARE MSB AD7233 INPUT SHIFT REGISTER (16 BITS) DAC LATCH (12 BITS DB0 DB1 LSB ...
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... DD SS APPLYING THE AD7233 Bipolar ( 5 V) Configuration The AD7233 provides an output voltage range from – without any external components. This configuration is shown in Figure 4. The data format is two's complement. The output code table is shown in Table I. If offset binary coding is required, then this can be done by inverting the MSB in soft- ware before the data is loaded to the AD7233 ...
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... Data on RXD is valid on the falling edge of TXD. The 87C51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7233, P3.3 is kept low after the first eight bits are LDAC transferred and a second byte of data is then transferred serially to the AD7233 ...
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... SCK. The 68HC11 transmits its se- rial data in 8-bit bytes with only eight falling clock edges occur- ring in the transmit cycle. To load data to the AD7233, PC7 is kept low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7233. When the second serial transfer is complete, the PC7 line is taken high ...