FS450 ETC2 [List of Unclassifed Manufacturers], FS450 Datasheet
FS450
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FS450 Summary of contents
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... Covered under US Patent # 5,862,268 and/or patents pending. ‡ 2 Note registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identical to Philips I bus. Description The i-Net TV FS450 is a fourth generation video scan converter. It accepts many input resolutions, rates and formats and converts them to NTSC or PAL standards compliant with SMPTE-170M and CCIR-656 standards ...
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Typical System Architectural Block Diagram ...
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... Level, Misc. Bits Reg. 8D (8A-8D)50 7. Design and Layout Considerations 7.1 Pixel Phase Lock Loop ...................... 52 7.2 Video Output Filters........................... 52 7.3 Analog Power Supply Bypassing, Filtering, and Isolation........................ 52 7.4 Power and Ground............................. 52 7.5 Interfacing to the FS450 in a Mixed Voltage Environment .......................... 53 7.5.1 Interfacing to the SIO bus.......... 53 8. Specifications 8.1 Absolute Maximum and Recommended Ratings............................................. 55 8 ...
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... D1 = 1N4148 2N3906 2N3904 .... 54 Figure 13: Package Outline & Dimensions ............ 58 JUNE, 2000, VERSION 1.2 PRELIMINARY PRODUCT DESCRIPTION Table 1: FS45x Pin Assignments......................... 11 Table 2: FS450 to GCC Pin Mapping.................... 12 Table 3: SAV and EAV Control Words.................. 24 Table 4: GCC Port Mapping (UIM_MOD)............... 24 Table 5: NCO_LOAD Control Bits......................... 34 TV ......... 9 Table 6: NOTCH_FRQ Values.............................. 50 Table 7: Typical Register Values for Various Standards ...
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... Figure 2: FS450 Functional Block Diagram 2.1 Oscillators and PLLs The FS450 synthesizes MHz clock off of the 27 MHz Television clock and supplies this clock (VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to the RGB data and Sync information. This clock has a 1½ Hz resolution and must be adjusted so the GCC scaled input data rate exactly matches the CCIR 656 data output rate ...
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... VGA_CLKOUT supplied by the FS450. The syncs are used inside the FS450 to capture the computer video and are regenerated to supply to external devices such as genlocked video from a DVD player or tuner. In full master mode, the FS450 supplies to the GCC horizontal and vertical sync in addition to the VGA pixel clock. ...
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... South American variations. The FS450 video encoder outputs NTSC M, J and PAL Combination N formats with 10 bits of resolution. Both Composite and S-Video outputs are available simultaneously. ...
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... FS450, FS451 3. Typical System Configurations There are 3 "typical" system configurations envisioned for the FS450: 1) GCC TV output only; 2) GCC or DVD output switched 3) Multiple digital video sources blended 3.1 GCC TV Output Only Synch Control VGA Synchs Color Space Converter RGB GCC Horz and Down ...
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... FS450, FS451 3.2 GCC or DVD Output Switched DVD Synch Control VGA Synchs Color Space Converter GCC RGB Horz and Vertical Down Scaler VGA Pixel Clock Figure 6: GCC or DVD output switched JUNE, 2000, VERSION 1.2 TV OSC 656 Flicker 656 Filter PLL 9 COPYRIGHT PRELIMINARY PRODUCT DESCRIPTION ...
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... FS450, FS451 3.3 Multiple Digital Video Sources Blended MPEG2 Decoder Video Frame CCIR 656 Decoder Memory Video Syncs 27 MHz Decoder Clk Crystal 27 MHz Encoder Clk Osc Sync Control VGA Syncs Color Space Converter VGA RGB Horz and Vertical Controller Down Scaler VGA Clk In ...
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... FS450, FS451 4. Pin Assignments 81 100 Pin Name Pin 1. R TV_CKIN 31 XTAL 32 33. R DDOSC 34. O SSOSC 5. G Reserved (GND) 35 Reserved (open) 36 37. O SSDA 38. R REF 39. O REF 10 40. O DDDA 11 ...
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... FS450, FS451 4.1 FS450 GCC Pin Mapping The following table maps the FS450/1 pins to the host GCC controller chip. Please contact your FOCUS representative to obtain the most up-to-date reference schematics before initiating a design. FS450 FS450/1 Intel Pin # Pin Name 82810 Pin Name ...
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... Television Clock XTAL Output. Buffered version of TV_CKIN. For use with a 27 MHz crystal. HSYNC Output. Output from FS450 to GCC to support slave mode operation. VSYNC Output. Output from FS450 to GCC to support slave mode operation. Reset. Active Low. Resets internal state machines and initializes default register values. ...
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... FS450, FS451 Pin Pin Type/Value Name Number Video Outputs Y/Red 12 analog video CVBS/Green 15 analog video C/Blue 17 analog video CSYNC 19 LVTTL output Voltage Reference V REF 8 +1.276 V R REF 9 390/780 C BYPASS 11 0.1 F CCIR 656 Input Port V656_IN 99,98,97,9 TTL input 7-0 6,94,93,92 (pull down) ,91 HBNK_IN 89 TTL input ...
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... FS450, FS451 Pin Pin Type/Value Name Number CCIR 656 Output Port V656_OUT 85,84,83,8 LVTTL output 7-0 1,80,79,77 ,76 HBNK_OUT 75 LVTTL output VBNK_OUT 73 LVTTL output FIELD_OUT 72 LVTTL output AHREF 69 LVTTL output AVREF 67 LVTTL output Serial Port SA10/7 25 TTL input (pull down TTL input (pull down) ...
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... FS450, FS451 6. Control Register Definitions 6.1 Control Register Map Function Reg. Bit # Name Input Horizontal Offset 0 7-0 IHO 7-0 1 2-0 IHO 10-8 Input Vertical Offset 2 7-0 IVO 7-0 3 2-0 IVO 10-8 Input Horizontal Width 4 7-0 IHW 7-0 5 1-0 IHW 9-8 Vertical Scaling Coefficient 6 7-0 VSC 7-0 7 7-0 VSC 15-8 Horizontal Down/Up Scaling Coefficients 8 7-0 HDSC 7-0 9 7-0 HUSC 7-0 Command Register C 7-0 CR ...
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... FS450, FS451 Function Reg. Bit # Name HSync Starting Edge 20 7-0 HSOUTST 7-0 21 2-0 HSOUTST 10-8 HSync Ending Edge 22 7-0 HSOUTEND 7-0 23 2-0 HSOUTEND 10-8 Flicker Filter Sharpness 24 4-0 SHP 4 Flicker Filter 26 4-0 FLK 4 Part Revision 32 7-0 REV 7-0 33 7-0 REV 15-8 Misc Register 34 7-0 MISC 7-0 35 7-0 MISC 15-8 FIFO Status Port Full/FIFO Status Port Empty 36 7-0 FIFOF 7-0 37 7-0 FIFOE 7-0 FIFO Latency ...
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... FS450, FS451 Function Reg. Bit # Name Chroma Frequency 40 7-0 CHR_FREQ 31-24 41 7-0 CHR_FREQ 23-16 42 7-0 CHR_FREQ 15-8 43 7-0 CHR_FREQ 7-0 Chroma Phase, Miscellaneous Bits 45 44 7-0 CHR_PHASE 7-0 45 1,0 MISC45 Miscellaneous Bits 46 7-0 MISC46 47 3-0 MISC47 HSync Width, Burst Width HSYNC_WID 48 7-0 7-0 BURST_WID 49 6-0 6-0 Backporch Width, CB Burst Level BPORCH 4A 7-0 7-0 CB_BURST 4B 7-0 7-0 CR Burst Level, Miscellaneous Bits 4D ...
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... FS450, FS451 Function Reg. Bit # Name ActiveLine 71 7-0 ACTIVELINE 10-3 72 2-0 ACTIVELINE 2-0 Chroma Phase 73 7-0 FIRST_LINE 7-0 Miscellaneous Bits 74, Sync Level 74 7-0 MISC74 75 7-0 SYNC_LVL 7-0 VBI Blank Level VBIBLNK_LVL 7C 7-0 9-2 VBIBLNK_LVL 7D 1-0 1-0 Reset, Encoder Version 7E 0 SOFT_RST 7F 7-0 ENC_VER 7-0 Miscellaneous Bits 80, WSS Clock Frequency (upper) 80 6-0 MISC80 81 7-0 WSS_CLK 11-4 WSS Clock Frequency (lower), WSS Data Field 1 (upper) ...
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... FS450, FS451 6.2 Control Register Definitions In the following definitions, range is defined as: {min value : [max value]} Please note that registers 0-3F use the little endian numbering scheme while registers 40-8D use the big endian numbering scheme. 6.2.1 IHO - Input Horizontal Offset Input Horizontal Offset Low ( ...
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... FS450, FS451 6.2.3 IHW - Input Horizontal Width Input Horizontal Width Low ( IHW IHW IHW 7 6 Input Horizontal Width High ( Reg Bit# Bit Name 5, 4 1-0, 7-0 IHW 9-0 Range 970} 6.2.4 VSC – Vertical Scaling Coefficient Vertical Scaling Coefficient ( VSC ...
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... FS450, FS451 6.2.5 HDSC, HUSC – Horizontal Down/Up Scaling Coefficients Horizontal Down Coefficient ( HDSC HDSC HDSC 7 6 Horizontal Up Coefficient ( HUSC HUSC HUSC 7 6 Reg Bit# Bit Name 8 7-0 HDSC 9 7-0 HUSC HDSC Range: { [-63]:0 } HUSC Range: { 0:127 } JUNE, 2000, VERSION 1 HDSC ...
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... Enable NCO Latch. When this bit is set, transfers the NCO words from the I2C registers into the NCO. The NCO synthesizes the VGA clock from the 27MHz FS450 clock. This clock must be adjusted so the VGA scaled input data rate exactly matches the CCIR 656 data output rate ...
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... FS450, FS451 Notes: VMI 656 Input Control: If the Video Module Interface (VMI) mode is specified, SAV and EAV commands are inserted into the CCIR601 data stream to coordinate down stream data processing. The SAV and EAV Control words have the following format: YC Data ...
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... Notes: FIFO Status: FS450 does not have a frame memory. In FS450 the scaled input data rate and the output data rates are the same. The FIFO takes up the slack during the asynchronous horizontal blanking interval of the input and output. The FIFO depth (1024) is only slightly larger that the 720 output pixels required to form a CCIR 601 data stream. ...
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... The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock (VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to the RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGA scaled input data rate exactly matches the CCIR 656 data output rate ...
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... The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock (VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to the RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGA scaled input data rate exactly matches the CCIR 656 data output rate ...
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... FS450, FS451 6.2.10 APO, ALO, AFO - Auxiliary Pixel, Line, and Field Offsets Auxiliary Pixel Offset Low (18 APO APO APO 7 6 Auxiliary Pixel Offset High (19 Auxiliary Line Offset (1A ALO ALO 6 Not Used (1B Auxiliary Field Offset (1C) ...
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... FS450, FS451 6.2.11 HSOUTWID, HSOUTST, HSOUTEND - HSync Out Width, Starting and Ending Edge HSync Out Width Low (1E HSOUTWID HSOUTWID HSOUTWID 7 6 HSync Out Width High (1F HSync Out Starting Edge Low (20 HSOUTST HSOUTST HSOUTST 7 6 HSync Out Starting Edge High (21) ...
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... The FIFO Latency register delays the Frame Start occurrence by 4x its value in 27MHz clock cycles. This delays the output 656 timing with respect to the input VGA timing and allows the FS450’s FIFO to fill appropriately before a FIFO read is initiated. ...
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... FS450, FS451 HREF 276 1 2 VREF PIXEL NO. 1 263 264 VREF PIXEL NO. 1 Figure 9: Auxiliary NTSC Reference Signals HREF 288 1 2 VREF PIXEL NO. 1 313 314 VREF PIXEL NO. 1 Figure 10: Auxiliary PAL Reference Signals JUNE, 2000, VERSION 1.2 1716 1440 265 ...
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... Three Line Average (FLK = 16), giving the user the best choice in filtering options. In addition to the variable vertical settings, the FS450 flicker filter has a sharpness function. This function is a two dimensional peaking function which accentuates the joint high vertical - high horizontal spatial frequencies (an " ...
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... FS450, FS451 6.2.13 REV - Revision Number Part Number (32 REV REV REV 7 6 Revision Number (33 REV REV REV 15 14 Reg Bit# Bit Name 33,32 15-0 REV 15-0 JUNE, 2000, VERSION 1 REV REV REV REV Description Revision Number [15:0]. Identifies the revision for software ID purposes (Rev Rev ...
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... The speed of the clock dither is sufficiently limited by the narrowband (around 5 kHz) PLL to prevent any problem with data transfers to the FS450. In fact, it provides an advantage for passing EMI certification and behaves much like off the shelf dithered clocks designed specifically for that purpose. ...
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... FS450, FS451 6.2.15 FIFOL, FIFOH - FIFO Status Port Full/Empty FIFO Status Port Full (36 FFOL FFOL FFOL 7 6 FIFO Status Port Empty (37 FFOH FFOH FFOH 7 6 Reg Bit# Bit Name 36 7-0 FFOL 7-0 37 7-0 FFOH Range 255} 6.2.16 FFO_LAT - FIFO Latency FIFO Latency Low (38) ...
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... FS450, FS451 6.2.17 VSOUTWID, VSOUTST, VSOUTEND - VSync Out Width, Starting and Ending Edge VSync Out Width Low (3A VSOUTWID VSOUTWID VSOUTWID 7 6 VSync Out Width High (3B VSync Out Starting Edge Low (3C VSOUTST VSOUTST VSOUTST 7 6 VSync Out Starting Edge High (3D) ...
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... FS450, FS451 6.2.18 CHR_FREQ - Chroma Subcarrier Frequency CHR_FREQ (40 CHR_FREQ CHR_FREQ CHR_FREQ 31 30 CHR_FREQ (41 CHR_FREQ CHR_FREQ CHR_FREQ 15 14 CHR_FREQ (42 CHR_FREQ CHR_FREQ CHR_FREQ 15 14 CHR_FREQ (43 CHR_FREQ CHR_FREQ CHR_FREQ 7 6 Reg Bit# Bit Name 40,41,42,43 CHR_FREQ all JUNE, 2000, VERSION 1.2 ...
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... FS450, FS451 6.2.19 Chroma Phase, Miscellaneous Bits 45 Chroma Phase (44 CHR_PHASE CHR_PHASE CHR_PHASE 7 6 Miscellaneous Bit Register 45 (45 Reg Bit# Bit Name CHR_PHASE 44 7 BYPYCLP 45 1 CLRBAR JUNE, 2000, VERSION 1 CHR_PHASE CHR_PHASE CHR_PHASE Description Pre-set Subcarrier Phase [7:0] ...
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... FS450, FS451 6.2.20 Miscellaneous Bits Registers 46 and 47 Miscellaneous Bits Register RGB_SETUP RGB_SYNC RGB_SYNC 2 Miscellaneous Bits Register Reg Bit# Bit Name 46 0 CVBS_EN YC_DELAY 46 3-1 46 6-4 RGB_SYNC 46 7 RGB_SETUP COMP_GAIN 47 1-0 COMP_YUV CHR_BW JUNE, 2000, VERSION 1 RGB_SYNC ...
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... FS450, FS451 6.2.21 HSync Width (48), Burst Width (49) HSync Width (48 HSYNC_WID HSYNC_WID HSYNC_WID 7 6 Burst Width (49 BURST_WID BURST_WID 6 Reg Bit# Bit Name HSYNC_WID 48 7-0 BURST_WID 49 6-0 6.2.22 Back Porch Width (4A), Cb Burst Amplitude (4B) Back Porch Width (4A BPORCH BPORCH BPORCH Burst Amplitude (4B) ...
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... FS450, FS451 6.2.23 Cr Burst Amplitude (4C), Miscellaneous Bits Register 4D Cr Burst Amplitude (4C CR_BURST CR_BURST CR_BURST 7 6 Miscellaneous Bits Register Reg Bit# Bit Name 4C 7-0 CR_BURST 4D 0 SLV_MOD 4D 1 SLV_THRS 6.2.24 Black Level (4E) Black Level (4E BLACK_LVL BLACK_LVL BLACK_LVL 9 8 Black Level (4F) ...
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... FS450, FS451 6.2.25 Blank Level (50) Blank Level (50 BLANK_LVL BLANK_LVL BLANK_LVL 9 8 Blank Level (51 Reg Bit# Bit Name BLANK_LVL 50, 51 7-0, 1-0 6.2.26 Number of Lines (57-58) Unused (56) Number of Lines (57 NUM_LINES NUM_LINES NUM_LINES 9 8 Number of Lines (58 Unused (59) ...
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... FS450, FS451 6.2.27 White Level (5E) White Level (5E WHITE_LVL WHITE_LVL WHITE_LVL 9 8 White Level (5F Reg Bit# Bit Name WHITE_LVL 5E, 5F 7-0, 1-0 6.2.28 Cb Color Saturation (60) Cb Color Saturation (60 CB_GAIN CB_GAIN CB_GAIN 7 6 Unused (61) Reg Bit# Bit Name 60 7-0 CB_GAIN 6.2.29 Cr Color Saturation (62) ...
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... FS450, FS451 6.2.30 Tint (65) Unused (64) Tint (65 TINT TINT TINT 7 6 Reg Bit# Bit Name 65 7-0 TINT 7-0 6.2.31 Width of Breezeway (69) Unused (68) Width of Breezeway (69 Reg Bit# Bit Name 69 4-0 BR_WAY 6.2.32 Front Porch (6C) Front Porch (6C FR_PORCH Unused (6D) Reg Bit# Bit Name ...
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... FS450, FS451 6.2.33 Active Video Line (71-72), First Video Line (73) Unused (70) Active Video Line (71 ACT_LINE ACT_LINE ACT_LINE 10 9 Active Video Line (72 First Video Line (73 1ST_LINE 1ST_LINE 1ST_LINE 7 6 Reg Bit# Bit Name 71, 72 7-0, 2-0 ACT_LINE 73 7-0 1ST_LINE JUNE, 2000, VERSION 1.2 ...
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... FS450, FS451 6.2.34 Miscellaneous Bits 74, Sync Level (75) Miscellaneous Bit Register UV_ORDER PAL_MODE CHR_BW Sync Level (75 SYNC_LVL SYNC_LVL SYNC_LVL 7 6 Reg Bit# Bit Name 74 0 VSYNC5 74 2-1 CPHASE 74 3 SYS625_50 74 4 INVERT_TOP 74 5 CHR_BW 74 6 PAL_MODE UV_ORDER 74 7 SYNC_LVL 75 7-0 JUNE, 2000, VERSION 1.2 ...
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... FS450, FS451 6.2.35 VBI Blank Level (7C) VBI Blank Level (7C VBIBL_LVL VBIBL_LVL VBIBL_LVL 9 8 VBI Blank Level (7D Reg Bit# Bit Name 7C, 7D 7-0, 1-0 VBIBL_LVL 6.2.36 SOFT_RST, ENC_VER - Encoder Soft Reset, Encoder Version Encoder Soft Reset (7E Encoder Version Number (7F) ...
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... FS450, FS451 6.2.37 Misc. Bit Reg. 80, WSS Clock (81-82), WSS Data F1(83-85) Miscellaneous Bit Register WSS_F1EN WSSF0_EN WSS Clock (81 WSS_CLK WSS_CLK WSS_CLK 11 10 WSS Clock (82 WSS Data Field 1 (83 WSS_DATF0 WSS_DATF0 WSS_DATF0 19 18 WSS Data Field 1 (84) ...
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... FS450, FS451 6.2.38 WSS Data Field 0(86-88), WSS Line Number Field 1 (89) WSS Data Field 0 (86 WSS_DATF0 WSS_DATF0 WSS_DATF0 19 18 WSS Data Field 0 (87 WSS_DATF0 WSS_DATF0 WSS_DATF0 11 10 WSS Data Field 0 (88 WSS Line Number Field 1 (89 ...
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... FS450, FS451 6.2.39 WSS Field 0 Line Number, WSS Level, Misc. Bits Reg. 8D (8A-8D) WSS Field 0 Line Number (8A WSS_LNF0 WSS_LNF0 WSS_LNF0 7 6 WSS Level (8B WSS_LVL WSS_LVL WSS_LVL 9 8 WSS Level (8C Miscellaneous Bits Register Reg ...
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... FS450, FS451 Hex Indx Register 40 CHR_FREQ 0x21f07c1f 44 CHR_PHASE 74 CPHASE 60 CR_GAIN 62 CB_GAIN 4C CR_BURST 4B CB_BURST 74 SYS625_50 74 VSYNC5 74 PAL_MODE 48 HSYNC_WID 49 BURST_WID 4A BPORCH 6C FRNT_PORCH 69 BREEZE_WAY 71 ACTIVELINE 50 BLANK_LVL 7C WSS_LVL 4E BLACK_LVL 5E WHITE_LVL 75 SYNC_LVL 57 LINE_FRAME Table 7: Typical Register Values for Various Standards JUNE, 2000, VERSION 1.2 NTSC PAL PAL-M ...
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... FS450, FS451 7. Design and Layout Considerations Careful circuit design and layout are key factors that insure a successful implementation of the FS450 in a product. The following guidelines will help insure that your design yields the best possible results. 7.1 Pixel Phase Lock Loop The analog supply for the Pixel PLL should always be clean and noise free to insure minimum jitter in the PLL ...
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... SIO bus and the FS450 are both 0.4 Volts. However, in heavily loaded SIO busses the output V always preserved. An easy way to regain the 0.7 Volt difference in the V the FS450’s input negative by a diode drop (D1). The diode can be biased by a long-tail resistor pair or a current source pair. Shown below is the long-tail pair: Figure 11. SIO Translation Using Long-tail Resistors The long-tail pair is a simple circuit but has the disadvantage of requiring higher voltage power supplies ...
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... FS450, FS451 To I2C Figure 12. SIO Translation Using Current Mirrors For applications with more than one supply, combinations of the above two circuits can be used. However, the simplest approach to this problem is to limit the loading on the SIO bus when possible. When this is not possible, some of the SIO passive loads can be replaced with active ones. This will increase the SIO access speed without increasing the SIO output low drive current ...
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... FS450, FS451 8. Specifications 8.1 Absolute Maximum and Recommended Ratings (beyond which the device may be damaged) 1 Parameter Power Supply Voltages V DD (Measured DDAD (Measured to V SSAD ) V DDPA and V DDPF (Measured to V SSPA and V SSPF ) V DDDA (Measured to V SSDA ) V SSAD , V SSPA , SSPA , V SSDA (delta) Digital Inputs 3 ...
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... FS450, FS451 8.2 Electrical Characteristics Parameter Power Supply Currents I DD3 3.3 volt Digital current I DDDA 3.3 volt Analog current I DDDA 3.3 volt Analog DAC current I DDOSC 3.3 volt Crystal Oscillator current I DDDPA 3.3 volt VGA PLL current I DDT 3.3 volt Total Current LVTTL Inputs and Outputs C I Input Capacitance ...
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... FS450, FS451 8.3 Switching Characteristics Parameter Clocks f CKIN TV Encoder Reference Clock Frequency f XTOL TV Reference Clock Frequency Tolerance t PWHT TV Reference Clock Pulse Width, HIGH t PWLT TV Reference Clock Pulse Width, LOW f PCKIN VGA Clock Positive Edge Frequency f NCKIN VGA Clock Negative Edge Frequency 4 f CORE ...
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... FS450, FS451 9. Mechanical Dimensions 9.1 100-Lead PQFP (KH) Package Symbol Inches Min. Max 100 ccc Figure 13: Package Outline & Dimensions JUNE, 2000, VERSION 1.2 Millimeters Notes Min. Max. Notes: 3.00 1. All dimensions and tolerances 0.05 - 2.55 2.75 2. Controlling Dimension is millimeters ...
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... FS450, FS451 10. Revision History October 13, 1999: First Release, V1.0. March 7, 2000: Second Release, V1.1: Throughout: changed encoder registers (40-8D) from little endian to big endian new patent referenced; p.12, corrected table by adding VGA_CKOUTTL, specifying proper clock for non-Intel designs, and proper Syncs for nVidia; p. 13, HSYNC_OUT & VSYNC_OUT are for Slave Mode ...
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FS401, FS402, FS403 600 Research Drive Wilmington, MA 01887 www.FOCUSinfo.com JUNE, 2000, VERSION 1.2 PRODUCT SPECIFICATION Phone: (978) 988-5888 Fax: (978) 988-7555 Email: info@FOCUSinfo.com 60 COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION REV. NO. 1.2 ...