ics8516 Integrated Device Technology, ics8516 Datasheet

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ics8516

Manufacturer Part Number
ics8516
Description
Differential-input Lvds-output 1 16 700-mhz Clock Buffer
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK
DISTRIBUTION CHIP
B
G
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
to-point solution for distributing clock signals over controlled
impedances of 100Ω.
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
8516FY
HiPerClockS™
IC S
LOCK
ENERAL
nCLK
CLK
OE1
OE2
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D
The ICS8516 is a low skew, high performance
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClock S ™
family of High Performance Clock Solutions from
ICS. The ICS8516 CLK, nCLK pair can accept
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
www.icst.com/products/hiperclocks.html
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
D
IFFERENTIAL
1
1
P
F
• Sixteen differential LVDS outputs
• CLK, nCLK pair can accept the following differential
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL,
• Translates any single-ended input signal to LVDS
• Multiple output enable inputs for disabling unused
• LVDS compatible
• Output skew: 90ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.4ns (maximum)
• Additive phase jitter, RMS: 148fs (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
SSTL, DCM) to LVDS levels without external bias networks
with resistor bias on nCLK input
outputs in reduced fanout applications
packages
EATURES
IN
A
GND
nQ5
nQ4
nQ3
nQ2
V
V
V
Q5
Q4
Q3
Q2
-
DD
DD
DD
SSIGNMENT
TO
7mm x 7mm x 1.4mm body package
-LVDS C
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
48-Lead LQFP
ICS8516
Y Package
Top View
LOCK
L
OW
D
ISTRIBUTION
S
KEW
REV. B FEBRUARY 21, 2006
ICS8516
36
35
34
33
32
31
30
29
28
27
26
25
DATA SHEET
, 1-
V
nQ10
Q10
nQ11
Q11
V
GND
nQ12
Q12
nQ13
Q13
V
DD
DD
DD
TO
C
ICS8516
-16
HIP
ICS8516

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ics8516 Summary of contents

Page 1

... ICS8516 provides a low power, low noise, point- to-point solution for distributing clock signals over controlled impedances of 100Ω. Dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516 ideal for those applications demanding well defined performance and repeatability ...

Page 2

... REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP ICS8516 ...

Page 3

... " ICS8516 ...

Page 4

... TSD C HIP µ A µ µ µ A µ A µ ICS8516 ...

Page 5

... µ µ ICS8516 ...

Page 6

... The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html -16 OW KEW LOCK ISTRIBUTION @ 155.52MHz (12kHz to 20MHz) = 148fs typical 10M ( REV. B FEBRUARY 21, 2006 TSD HIP 100M ICS8516 ...

Page 7

... NPUT PART 1 nQx Qx PART 2 nQy ART TO ART Clock 20% Outputs UTPUT ISE ALL www.icst.com/products/hiperclocks.html KEW LOCK ISTRIBUTION Cross Points V CMR L EVEL tsk(pp) KEW 80% 80% 20 IME REV. B FEBRUARY 21, 2006 -16 TSD HIP V OD ICS8516 ...

Page 8

... KEW - -LVDS LOCK ISTRIBUTION V DD out LVDS out V S OLTAGE ETUP V DD LVDS UTPUT HORT CIRCUIT URRENT LVDS EAKAGE ETUP REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP V /Δ out I OSD out S ETUP OFF ICS8516 ...

Page 9

... All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. www.icst.com/products/hiperclocks.html KEW - -LVDS LOCK ISTRIBUTION EVELS = 3.3V, V_REF should be 1.25V DD CLKx nCLKx D I IFFERENTIAL NPUT : UTPUT REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP ICS8516 ...

Page 10

... LVPECL 2B CLK/nCLK LOCK NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 2D CLK/nCLK LOCK NPUT 3.3V LVDS D RIVER REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP Input D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY ICS8516 ...

Page 11

... LVDS_Driver S E CHEMATIC XAMPLE Figure 4 shows a schematic example of ICS8516. In this ex- ample, the input is driven by an LVDS driver. For LVDS buffer recommended to terminate the unused outputs for better LVDS_Driver Ohm Ohm (U1-1) VDD=3 ...

Page 12

... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8516 is: 1821 8516FY IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP D - IFFERENTIAL ...

Page 13

... ° REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP ICS8516 ...

Page 14

... R REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP ° ° ° ° ° ° ° ° ICS8516 ...

Page 15

... REV. B FEBRUARY 21, 2006 , 1- -16 TO TSD C HIP ICS8516 ...

Page 16

... ICS8302-01 ICS1890 ICS1527 ICS8516 MK1491-14 ICS280 Video Clock Synthesizer LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP Auto-Negotiation Advertisement Register (register 4 [0x04]) LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT OPTi ACPI Firestar Clock Source TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks ...

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