ics8624 Integrated Device Technology, ics8624 Datasheet
ics8624
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ics8624 Summary of contents
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... Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8624 is a high performance, 1-to-5 ICS Differential-to-HSTL zero delay buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8624 has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels ...
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... www.icst.com/products/hiperclocks.html 2 ICS8624 KEW - -HSTL ERO ELAY ...
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... ÷ 4 ÷ 4 ÷ 4 ÷ 8 www.icst.com/products/hiperclocks.html 3 ICS8624 KEW - -HSTL ERO ELAY ...
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... www.icst.com/products/hiperclocks.html 4 ICS8624 KEW - -HSTL ERO ELAY = 1.8V±0.2V 0°C 70° ...
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... www.icst.com/products/hiperclocks.html 5 ICS8624 KEW - -HSTL ERO ELAY = 0°C 70° ...
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... Clock 20% Outputs is the average mean O R UTPUT ISE nCLK0, V nCLK1 DDO 2 CLK0, CLK1 nQ0:nQ4 Q0:Q4 P ROPAGATION www.icst.com/products/hiperclocks.html 6 ICS8624 KEW - -HSTL ERO ELAY NFORMATION Cross Points I L NPUT EVEL ➤ ➤ ➤ cycle n cycle n jit(cc) = cycle n – ...
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... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8624 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...
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... HiPerClockS Input D F 3B. H NPUT RIVEN BY IGURE RIVER 3.3V 3.3V LVDS_Driv er CLK nCLK HiPerClockS Input 3D. H NPUT RIVEN BY IGURE www.icst.com/products/hiperclocks.html 8 ICS8624 KEW - -HSTL ERO ELAY 3. Ohm CLK Ohm nCLK HiPerClockS Input ...
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... Circuit Systems, Inc AYOUT UIDELINE The schematic of the ICS8624 layout example is shown in Figure 4A. The ICS8624 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system VDD SP = Space (i.e. not intstalled) ...
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... The matching termination resistors should be located as close to the receiver input pins as possible 4B. PCB IGURE OARD AYOUT OR www.icst.com/products/hiperclocks.html 10 ICS8624 KEW - -HSTL ERO ELAY GND VDDO VDD VDDA VIA 50 Ohm Traces ICS8624 REV. C JUNE 15, 2004 -5 TO UFFER ...
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... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8624 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...
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... Pd_H = (1V/50Ω) * (2V - 1V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8624BY D IFFERENTIAL V DDO Q1 5. HSTL IGURE RIVER IRCUIT AND www.icst.com/products/hiperclocks.html 12 ICS8624 KEW - -HSTL ERO ELAY V OUT RL 50Ω ERMINATION REV. C JUNE 15, 2004 ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8624 is: 1565 8624BY D IFFERENTIAL R I ELIABILITY ...
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... ° 0 www.icst.com/products/hiperclocks.html 13 ICS8624 KEW - -HSTL ERO ELAY ...
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... L " " " " www.icst.com/products/hiperclocks.html 14 ICS8624 KEW - -HSTL ERO ELAY ° ...
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... L " " www.icst.com/products/hiperclocks.html 16 ICS8624 KEW - -HSTL ERO ELAY ...