ics9db108 Integrated Device Technology, ics9db108 Datasheet
ics9db108
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ics9db108 Summary of contents
Page 1
... DIF_0 DIF_0# 9 GND 10 VDD 11 DIF_1 12 DIF_1# 13 OE_1 14 OE_2 15 DIF_2 16 DIF_2# 17 GND 18 VDD 19 DIF_3 20 DIF_3# 21 BYPASS#/PLL 22 SCLK 23 SDATA 24 48-pin SSOP & TSSOP ICS9DB108 48 VDDA 47 GNDA 46 IREF 45 LOCK 44 OE_7 43 OE_4 42 DIF_7 41 DIF_7# 40 GND 39 VDD 38 DIF_6 37 DIF_6# 36 OE_6 35 OE_5 34 DIF_5 33 DIF_5# 32 GND 31 VDD ...
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... Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 2 ICS9DB108 ...
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... This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 3 ICS9DB108 ...
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... ICS9DB108 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB108 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. ICS9DB108 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements. ...
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... DD input clock stabilization or de- assertion of PD# to 1st clock Triangular Modulation DIF output enable after SRC_Stop# de-assertion DIF output enable after PD# de-assertion Fall time of PD# and SRC_STOP# Rise time of PD# and SRC_STOP# 5 ICS9DB108 Units ° C °C °C V TYP MAX UNITS NOTES ...
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... Measurement from differential wavefrom V = 50% T PLL mode, Measurement from differential wavefrom BYPASS mode as additive jitter = 2.32mA and V REF OH REF OH 6 ICS9DB108 MIN TYP MAX UNITS Ω 3000 660 850 mV -150 150 1150 mV -300 250 550 mV 140 mV 0 ppm 4 ...
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... Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9DB108 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • ...
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... Control Function Type Output Control RW Disable Output Control RW Disable Output Control RW Disable Output Control RW Disable Output Control RW Disable Output Control RW Disable Output Control RW Disable Output Control RW Disable 8 ICS9DB108 0 1 PWD Hi-Z 0 Hi-Z 0 Reserved X Reserved X Reserved X 1 ZDB PWD Enable 1 Enable 1 ...
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... Reserved Reserved RW Reserved Reserved RW Reserved Reserved RW Reserved RW Reserved Reserved RW Reserved Reserved Reserved RW Reserved Reserved RW Reserved Reserved RW Control Function Type REVISION VENDOR ICS9DB108 1 PWD PWD PWD - ...
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... Device Device Device Device Device Control Type 0 Function Writing to this RW - register configures RW - how many bytes RW - will be read back ICS9DB108 1 PWD Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 1 PWD - ...
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... SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion. PWRDWN# DIF DIF# 0723F—12/17/07 (Not recommended for new designs) and DIF# tri-stated. If the PD# drive mode bit is REF Tstable <1mS Tdrive_PwrDwn# <300uS, >200mV 11 ICS9DB108 ...
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... DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate Driven) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0723F—12/17/07 (Not recommended for new designs) DIF# is not driven, but pulled low by the termination. When the REF. 1mS 1mS 12 ICS9DB108 ...
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... SRC_STOP_3 (SRC_Stop = Driven Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0723F—12/17/07 (Not recommended for new designs) 1mS 1mS 13 ICS9DB108 ...
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... Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS = Standard Device 14 ICS9DB108 In Millimeters In Inches COMMON DIMENSIONS MAX MIN 2.80 .095 0.40 ...
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... Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS = Standard Device 15 ICS9DB108 (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX ...
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... Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description E 10/26/05 Updated LF Ordering Information LN. F 12/17/00 Updated SMBus Serial Interface Information. 0723F—12/17/07 (Not recommended for new designs) 16 ICS9DB108 Page # 14 ...