ics9fg107 Integrated Device Technology, ics9fg107 Datasheet
ics9fg107
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ics9fg107 Summary of contents
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... It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps. ICS9FG107 also provides a copy of the reference clock and 333 MHz PCI output clocks. Frequency selection can be accomplished via strap pins or SMBus control. ...
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... ICS9FG107 100.00 125.00 133.33 166.67 200.00 266.66 333.33 400.00 100.00 125.00 133.33 166.67 200.00 266.66 333.33 400.00 REV F 08/21/07 ...
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... Power supply, nominal 3.3V OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active high input for enabling output tri-state outputs, 1= enable outputs I/O Data pin for SMBus circuitry, 3.3V tolerant. IN Clock pin of SMBus circuitry, 5V tolerant. TM CPU, PCI-Express & SATA Clocks 3 DESCRIPTION ICS9FG107 REV F 08/21/07 ...
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... This pin requires a fixed precision resistor tied to OUT ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. TM CPU, PCI-Express & SATA Clocks 4 DESCRIPTION ICS9FG107 REV F 08/21/07 ...
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... ICS9FG107 Programmable FTG for Differential P4 General SMBus serial interface information for the ICS9FG107 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... Disable Enable Type Stop Low Enable RW Free-run Stop-able RW Free-run Stop-able RW Free-run Stop-able RW Free-run Stop-able RW Free-run Stop-able RW Free-run Stop-able RW Free-run Stop-able ICS9FG107 PWD Pin 27 Pin 5 Pin 44 Pin 7 Pin Pin 45 PWD PWD REV F 08/21/07 ...
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... On R RESERVED R RESERVED R Down Center Type Type RESERVED R RESERVED R RESERVED R RESERVED R RESERVED R RESERVED R RESERVED R RESERVED ICS9FG107 PWD Pin 27 Pin 5 Pin 44 Pin 7 Pin Pin 45 PWD PWD REV F 08/21/07 ...
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... Control Function BC7 BC6 Writing to this BC5 register will configure BC4 how many bytes will BC3 be read back, default BC2 bytes. BC1 BC0 TM CPU, PCI-Express & SATA Clocks 8 Type ICS9FG107 PWD REV F 08/21/07 ...
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... DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV. DIF_Stop# DIF DIF# DIF Internal TM TM IDT /ICS Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks Tdrive_DIF_Stop, 10nS >200mV TM CPU, PCI-Express & SATA Clocks 9 ICS9FG107 REV F 08/21/07 ...
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... VDD F TM CPU, PCI-Express & SATA Clocks 10 Units V V ° C °C °C V MIN TYP MAX UNITS NOTES 0 0.3 0 -200 250 200 1 1 ICS9FG107 MHz 1,2 kHz REV F 08/21/07 ...
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... ICS9FG107 REV F 08/21/07 NOTES 1,2 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1 ...
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... Min Mean 52 53 Min Mean 2 23 -25 -5 -24 -2 -22 -2 -50 -29 -49 -30 TM CPU, PCI-Express & SATA Clocks 12 Max NOTES 35 1 Max - -32 1 -35 1 Max NOTES 52 1 Max ICS9FG107 REV F 08/21/07 ...
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... MIN TYP MAX UNITS Notes -300 0 300 ppm 69.8270 69.8413 69.8550 ns 39.9880 40.0000 40.0120 ns 2.4 V 0.4 V - 160 250 ps ICS9FG107 Notes 1 1,2 1 REV F 08/21/07 ...
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... Dimension or Value Unit Figure 2 min to 16 max inch 1 1.8 min to 14.4 max inch 1 Dimension or Value Unit Figure 0. max inch 2 0.225 min to 12.6 max inch 2 L4 L4’ PCI Ex Board Down Device REF_CLK Input L4 L4’ PCI Ex Add In Board REF_CLK Input ICS9FG107 REV F 08/21/07 ...
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... R1a L4’ L2’ R1b R2a R2b L3’ L3 Note 3.3 Volts R5a R5b Cc Cc R6a R6b TM CPU, PCI-Express & SATA Clocks 15 Figure 3. Note ICS874003i-02 input compatible Standard LVDS R4 Down Device REF_CLK Input PCIe Device REF_CLK Input ICS9FG107 REV F 08/21/07 ...
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... SEE VARIATIONS 10.03 10.68 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 ICS9FG107 In Inches MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° ...
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... BASIC E1 6.00 6.20 e 0.50 BASIC L 0.45 0.75 N SEE VARIATIONS a 0° 8° aaa -- 0.10 D mm. N MIN MAX 48 12.40 12.60 ICS9FG107 In Inches COMMON DIMENSIONS MIN MAX -- .047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0° ...
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... ICS9FG107 Programmable FTG for Differential P4 Revision History Rev. Issue Date Description D 08/06/07 Updated Differential Output Skew Specifications E 08/08/07 Updated Differential Output Skew Specifications F 08/21/07 Updated Differential Output Skew Specifications TM TM CPU, PCI-Express & SATA Clocks Innovate with IDT and accelerate your future networks. Contact: www ...