IDT70121 Integrated Device Technology, IDT70121 Datasheet

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IDT70121

Manufacturer Part Number
IDT70121
Description
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
Manufacturer
Integrated Device Technology
Datasheet

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FEATURES:
• High-speed access
• Low-power operation
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
• On-chip port arbitration logic (IDT70121 only)
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V ( 10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40 C to +85 C) is avail-
FUNCTIONAL BLOCK DIAGRAM
NOTES:
1. 70121 (MASTER):
2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
bits or more using SLAVE IDT70125 chip
– Commercial: 25/35/45/55ns (max.)
– IDT70121/70125S
– IDT70121/70125L
BUSY
INT
able, tested to military electrical specifications
Integrated Device Technology, Inc.
BUSY
stated push-pull
output.
70125 (SLAVE):
BUSY
INT
output.
Active: 500mW (typ.)
Standby: 5mW (typ.)
Active: 500mW (typ.)
Standby: 1mW (typ.)
is totem-pole
flag for port-to-port communication
is non-tri-
is input.
output flag on Master;
I/O
0L
BUSY
- I/O
R/
INT
A
OE
CE
A
W
10L
0L
8L
L
L
(1,2)
(2)
L
L
L
BUSY
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
input on Slave
Decoder
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
Address
R/
CE
OE
W
L
L
L
11
Control
I/O
6.10
ARBITRATION
DESCRIPTION:
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by
the on-chip circuitry of each port to enter a very low standby
power mode.
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
SEMAPHORE
INTERRUPT
MEMORY
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Both devices provide two independent ports with separate
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
ARRAY
LOGIC
Control
I/O
11
Decoder
Address
CE
OE
R/
W
R
R
R
IDT70121S/L
IDT70125S/L
OCTOBER 1996
2654 drw 01
CE
R/
OE
BUSY
CE
DSC-2654/4
1
I/O
INT
W
A
A
, permits
R
R
11R
0R
R
0R
R
R
-I/O
(2)
(1,2)
8R

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IDT70121 Summary of contents

Page 1

... STATIC RAM WITH BUSY & INTERRUPT DESCRIPTION: The IDT70121/IDT70125 are high-speed Dual-Port Static RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-Port RAM “MASTER” Dual-Port RAM together with the IDT70125 “SLAVE” Dual-Port in 18- bit-or-more word width systems. Using the IDT MASTER/ ...

Page 2

... Vcc + 0.5V for more than 25% of the cycle time or TERM 10ns maximum, and is limited to < 20mA for the period of V 0.5V. retention capability with each port typically consuming 200 W from a 2V battery. The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE OE 46 ...

Page 3

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter ( Input Leakage Current LI ( Output Leakage Current LO ...

Page 4

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT DATA RETENTION CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) ...

Page 5

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT TIMING WAVEFORM OF READ CYCLE NO. ...

Page 6

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Write Cycle (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW ...

Page 7

... AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master IDT70121 Only) BUSY t Access Time from Address BAA BUSY ...

Page 8

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND ADDR ' 'A' DATA IN 'A' (1) t APS ADDR 'B' BUSY 'B' DATA OUT 'B' NOTES: ...

Page 9

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDR L and APS CE L BUSY L NOTES: 1. All timing is the same for ...

Page 10

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT TIMING WAVEFORM OF INTERRUPT MODE INTERRUPT SET ADDRESS ADDR 'A' ( 'A' t INS INT 'B' NOTES:. 1. All timing is the same ...

Page 11

... Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70121 RAM the busy pin is an output of the part, and the busy pin is an input of the IDT70125 as shown in Figure 3. ...

Page 12

IDT 70121/70125S/L HIGH-SPEED DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT ORDERING INFORMATION IDT XXXXX A 999 Device Power Speed Type A A Package Process/ Temperature Range Blank 70121 70125 6.10 ...

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