IDT70T3509M Integrated Device Technology, IDT70T3509M Datasheet
IDT70T3509M
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IDT70T3509M Summary of contents
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... Dout27-35_L Dout27-35_R 1024K x 36 MEMORY ARRAY Din_L Din_R Counter/ ADDR_R ADDR_L Address Reg INTERRUPT CE1 L LOGIC ( CONTROL LOGIC 1 IDT70T3509M ...
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... High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Description: The IDT70T3509M is a high-speed 1024K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Pin Configuration (1,2,3,4) 08/03/ TDI A A 19L 17L I/O NC TDO A 18L 18L I/O I 18R 19L SS 16L PIPE/ FT I/O I/O I/O 20R 19R 20L I/O I/O I/O V 21R 21L 22L DDQL F1 F2 ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Pin Names Left Port Right Port Chip Enables (Input R/W R/W Read/Write Enable (Input Output Enable (Input Address (Input) 0L 19L 0R 19R I/O - I/O I/O - I/O Data Input/Output 0L 35L 0R 35R CLK ...
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... When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 7. Address A must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Recommended Operating Temperature and Supply Voltage Commercial Industrial NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions with V Symbol NOTES select operation at 2.5V levels on the I/Os and controls of a given port, the OPT ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Absolute Maximum Ratings Symbol Rating V V Terminal Voltage TERM with Respect to GND DD ( Terminal Voltage TERM DDQ (V ) with Respect to GND DDQ V (2) Input and I/O Terminal TERM (INPUTS and I/O's) Voltage with Respect to GND ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active (6) I Standby Current SB1 L (Both Ports - TTL Level Inputs) ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT ∆ tCD (Typical, ns) - 3.3V/2.5V) DDQ GND to 3 0V/GND to 2.4V . GND to 3.0V/GND to 2.4V 2ns 1 ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) CH1 t Clock Low Time (Flow-Through) CL1 ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (1,2) (FT/PIPE = CYC2 t CH2 CLK (4) ADDRESS An (1 Latency) DATA OUT (1) OE Timing Waveform of Read Cycle for Flow-Through Output ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A " ADDRESS "A" MATCH DATA VALID IN"A" CLK "B" R/W "B" ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK (3) An ADDRESS DATA IN (1) DATA OUT READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK BEn (3) An ADDRESS DATA IN t CD1 (1) DATA OUT READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) ...
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... there is no address change via ADS = V IL remains constant for subsequent clocks. 3. Address A must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 19 value while for physical addresses 80000 19 sure that A is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation. As shown this ...
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... For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations. 7. Address A must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 19 value while for physical addresses 80000 ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Waveform of Interrupt Timing CLK R ADDRESS (3) L FFFFF (1) L INT R CLK R CE (1) R R/W R ADDRESS (3) R NOTES and All timing is the same for Left and Right ports. ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Timing Waveform - Entering Sleep Mode R/W Timing Waveform - Exiting Sleep Mode R/W OE DATA OUT (4) NOTES IH. 2. All timing is same for Left and Right ports has to be deactivated ( three cycles prior to asserting ZZ (ZZx = V ...
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... Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. Sleep Mode The IDT70T3509M is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions ...
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... TMS TRST Register Sizes, and System Interface Parameter tables. Specifically, all serial commands must be issued to the IDT70T3509M in the following sequence: Array D, Array C, Array B, Array A. Please reference Application Note AN-411, "JTAG Testing of Multichip Modules" for specific instructions on performing JTAG testing on the IDT70T3509M. AN-411 is available at www ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Identification Register Definitions Value Instruction Field Instruction Field Array D Array C Array D Revision Number (31:28) 0x0 Revision Number (63:60) IDT Device ID (27:12) 0x333 IDT Device ID (59:44) IDT JEDEC ID (11:1) 0x33 IDT JEDEC ID (43:33) ID Register Indicator Bit (Bit Register Indicator Bit (Bit 32) ...
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... IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Ordering Information XXXXX A 999 A IDT Device Power Speed Package Type NOTES: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office 3 ...