IDT70V28 Integrated Device Technology, Inc., IDT70V28 Datasheet
IDT70V28
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IDT70V28 Summary of contents
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... Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70V28 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device Functional Block Diagram ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Description The IDT70V28 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT70V28 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word system. Using the IDT MASTER/SLAVE Dual- ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Pin Names Left Port Right Port Chip Enables R/W R/W Read/Write Enable Output Enable Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output 0L 15L 0R 15R SEM SEM Semaphore Enable ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Truth Table I – Chip Enable < 0. >V -0.2V CC (3) X NOTES: 1. Chip Enable references are shown above with the actual and ' CMOS standby requires ' either < 0.2V or >V Truth Table II – Non-Contention Read/Write Control ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTES: < Vcc 2.0V, input leakages are undefined. ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT BUSY OUT Timing of Power-Up Power-Down CE ( NOTES: 1 ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t Output Enable Access Time ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE (9,10 SEM ( ( R/W DATA OUT DATA IN Timing Waveform of Write Cycle No Controlled Timing ADDRESS (9,10 SEM ( ( R/W DATA IN NOTES and during all address transitions ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES and for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" t APS ADDR " ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" CE "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V28 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and is not met, either BUSY enable inputs of this port ...
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... BUSY signal as a write inhibit signal. Thus on the IDT70V28 RAM the BUSY pin is an output if the part is used and the BUSY pin is an input if the part used master (M/S pin = V ...
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... The eight semaphore flags reside within the IDT70V28 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip ...
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... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers. Datasheet Document History: 08/01/99: Initial Public Offering 01/10/01: Page 3 Increased storage temperature parameter ...