IDT70V3579S Integrated Device Technology, IDT70V3579S Datasheet
IDT70V3579S
Available stocks
Related parts for IDT70V3579S
IDT70V3579S Summary of contents
Page 1
... Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R Dout18-26_L Dout18-26_R Dout27-35_L Dout27-35_R 32K x 36 MEMORY ARRAY Din_L Din_R ADDR_L ADDR_R 1 IDT70V3579S R I I/O 35R CLK R A 14R Counter Address CNTRST R Reg. ...
Page 2
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times ...
Page 3
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM I 18L I/O I 18R 19L I/O I/O I/O 20R 19R V 20L I/O I/O I/O V 21R 21L 22L DDQL I/O I/O I/O V 23L 22R 23R DDQL G1 G2 ...
Page 4
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM 1 I/O 19L 2 I/O 19R 3 I/O 20L 4 I/O 20R 5 V DDQL I/O 21L I/O 8 21R I/O 9 22L 10 I/O 22R V 11 DDQR I/O 13 23L 14 I/O 23R I/O 15 24L I/O 16 24R V 17 DDQL I/O 19 25L I/O 20 25R I/O 21 26L I/O 22 26R V 23 DDQR ...
Page 5
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable Address 0L 14L 0R 14R I/O - I/O I/O - I/O Data Input/Output 0L 35L 0R 35R CLK CLK Clock L R ADS ADS ...
Page 6
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Previous Addr (6) Address Address Used CLK NOTES: 1. "H" "L" "X" = Don't Care. IH, IL, 2. Read and write operations are controlled by the appropriate setting of R/ ...
Page 7
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter Conditions C Input Capacitance IN (3) C Output Capacitance V OUT NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from from ...
Page 8
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Sym bol Param eter CE and CE I Dynam ic Ope rating DD L Current (B oth Outputs Disabled , (1) P orts A ctiv MAX tand by Curre nt SB1 L (1) ( orts - TTL MAX Inp uts) ...
Page 9
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50 DATA OUT Figure 1. AC Output Test load tCD (Typical, ns) ...
Page 10
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Pipelined) CH2 t Clock Low Time (Pipelined) CL2 t Clock Rise Time R t Clock Fall Time F t Address Setup Time SA t Address Hold Time ...
Page 11
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM t CYC2 t CH2 CLK (0- (4) ADDRESS An (1 Latency) DATA OUT (1) OE NOTES asynchronously controlled; all other inputs are synchronous to the rising clock edge. ...
Page 12
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM CLK R ADDRESS L MATCH DATA VALID INL t CO CLK R R ADDRESS MATCH R DATA OUTR NOTES and ADS = V , CNTEN, and CNTRST = ...
Page 13
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK (3) An ADDRESS DATA IN (1) DATA OUT OE READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...
Page 14
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (7) An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL Ax ADDRESS ADS ...
Page 15
... LOW on CE for one clock cycle will power 0 1 down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V3579s for depth expansion configurations. Two cycles are required with CE LOW and CE HIGH to re-activate the outputs. 1 ...
Page 16
... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM IDT XXXXX A 99 Device Power Speed Package Type 12/9/98: Initial Public Release 3/12/99: Added fpBGA package 4/28/99: Fixed typo on page 10 6/8/99: Changed drawing format Page 2 Changed package body dimensions 6/15/99: Page 5 Deleted note 6 for Table II 8/4/99: Page 6 Improved power numbers 10/4/99: Upgraded speed to 133MHz, added 2 ...