IDT70V9289L Integrated Device Technology, IDT70V9289L Datasheet

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IDT70V9289L

Manufacturer Part Number
IDT70V9289L
Description
High-speed 3.3v Synchronous Pipelined Dual-port Static
Manufacturer
Integrated Device Technology
Datasheet

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I/O
©2000 Integrated Device Technology, Inc.
I/O
FT
8L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
Low-power operation
– IDT70V9289L
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
CE
CE
0L
-I/O
/PIPE
-I/O
R/
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
0L
1L
UB
OE
LB
15L
W
7L
CNTRST
L
L
L
L
L
CNTEN
CLK
ADS
A
A
15L
0L
L
L
L
L
0/1
0/1
0
1
1b 0b
Counter/
Address
b a
Reg.
1a 0a
HIGH-SPEED 3.3V 64K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Control
I/O
MEMORY
ARRAY
1
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP)
address inputs
Control
I/O
Counter/
Address
0a 1a
Reg.
a
b
0b 1b
0/1
1
0
0/1
PRELIMINARY
IDT70V9289L
4855 drw 01
R/
LB
OE
I/O
UB
FT
A
A
CLK
ADS
CNTEN
CNTRST
I/O
15R
0R
W
R
/PIPE
DSC-4855/1
8R
R
R
0R
CE
CE
R
R
R
-I/O
-I/O
0R
1R
R
R
R
15R
7R

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IDT70V9289L Summary of contents

Page 1

... True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns (max.) Low-power operation – IDT70V9289L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features ...

Page 2

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM The IDT70V9289 is a high-speed 64K x 16 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. ...

Page 3

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM Left Port Right Port CE CE Chip Enables CE CE 0L, 1L 0R, 1R R/W R/W Read/Write Enable Output Enable Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output 0L 15L 0R 15R CLK CLK Clock Upper Byte Select ...

Page 4

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM Previous Addr Address Address Used CLK NOTES: 1. "H" "L" "X" = Don't Care. IH, IL LB, UB, and and R Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. ...

Page 5

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE Vcc < 2.0V input leakages are undefined. Symbol Parameter Test Condition CE and CE I Dynamic Operating ...

Page 6

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 435 Figure 1. AC Output Test load. , tCD 1 tCD 2 (Typical, ns) Figure 3. Typical Output Derating (Lumped Capacitive Load). ...

Page 7

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM Symbol t Clock Cycle Time (Flow-Through) CYC1 (2) t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) CH1 t Clock Low Time (Flow-Through) CL1 (2) t Clock High Time (Pipelined) CH2 (2) t Clock Low Time (Pipelined) ...

Page 8

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM FT t CH1 CLK UB (5) ADDRESS An DATA OUT t CKLZ ( CH2 CLK UB ...

Page 9

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM t CYC2 t CH2 CLK ADDRESS (B1 0(B1) DATA OUT(B1 ADDRESS (B2) CE 0(B2 DATA OUT(B2) CLK "A" R/W "A" ADDRESS "A" MATCH ...

Page 10

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM t CYC2 t CH2 CLK UB (4) An ADDRESS DATA IN (2) DATA OUT t CYC2 t CH2 CLK UB ...

Page 11

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM t CYC1 t CH1 CLK UB (4) An ADDRESS DATA IN t CD1 (2) DATA OUT t CYC1 t CH1 CLK UB, LB ...

Page 12

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK ADDRESS t t SAD HAD ADS CNTEN ( DATA OUT READ EXTERNAL ADDRESS t CYC1 t t CH1 CL1 CLK ADDRESS t t SAD HAD ADS ...

Page 13

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM t CH2 CLK ADDRESS (3) INTERNAL ADDRESS t t SAD HAD ADS (7) CNTEN DATA IN WRITE EXTERNAL ADDRESS t CYC2 t t CH2 CLK (4) ADDRESS (3) INTERNAL (6) Ax ADDRESS W R/ ADS CNTEN t t SRST HRST ...

Page 14

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM The IDT70V9289 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal ...

Page 15

... IDT70V9289L High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM IDT XXXXX A 99 Device Power Speed Type NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. "PRELIMINARY" datasheets contain descriptions for products that are in early release. ...

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