IDT7134 Integrated Device Technology, IDT7134 Datasheet

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IDT7134

Manufacturer Part Number
IDT7134
Description
High-speed 4k X 8 Dual-port Static Ram With Semaphore
Manufacturer
Integrated Device Technology
Datasheet

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Features
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Functional Block Diagram
©2006 Integrated Device Technology, Inc.
I/O
A
High-speed access
– Military: 25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
– IDT7134SA
– IDT7134LA
0L
0L
Active: 700mW (typ.)
Standby: 5mW (typ.)
Active: 700mW (typ.)
Standby: 1mW (typ.)
- I/O
- A
R/W
OE
CE
11L
L
L
7L
L
DECODER
ADDRESS
CONTROL
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
I/O
MEMORY
ARRAY
1
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Fully asynchronous operation from either port
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
CONTROL
I/O
DECODER
ADDRESS
JANUARY 2006
IDT7134SA/LA
I/O
A
R/W
OE
CE
0R
0R
R
- A
R
R
- I/O
2720 drw 01
DSC-2720/13
11R
7R

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IDT7134 Summary of contents

Page 1

... High-speed access – Military: 25/35/45/55/70ns (max.) – Industrial: 25/35/55ns (max.) – Commercial: 20/25/35/45/55/70ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7134SA Active: 700mW (typ.) Standby: 5mW (typ.) – IDT7134LA Active: 700mW (typ.) Standby: 1mW (typ.) Functional Block Diagram ...

Page 2

... The IDT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL- PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability ...

Page 3

... IDT7134SA/LA High-Speed Dual-Port Static SRAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to +150 STG Temperature (3) P Power 1.5 T Dissipation I DC Output 50 OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 4

... IDT7134SA/LA High-Speed Dual-Port Static SRAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating CC IL Current Outputs Disabled (3) (Both Ports Active MAX CE and CE I Standby Current SB1 L (Both Ports - TTL ( MAX Level Inputs) ...

Page 5

... IDT7134SA/LA High-Speed Dual-Port Static SRAM Data Retention Characteristics Over All Temperature Ranges (LA Version Only 0.2V Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Dese lect to Data Retention Time CDR (3) t Operation Recovery Time R NOTES 2V +25° ...

Page 6

... IDT7134SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change ...

Page 7

... IDT7134SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS PREVIOUS DATA VALID DATA OUT Timing Waveform of Read Cycle No. 2, Either Side CE OE DATA OUT CURRENT I SB NOTES: 1. Timing depends on which signal is asserted last CE. ...

Page 8

... IDT7134SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time ...

Page 9

... IDT7134SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write with Port-to-Port Read ADDR "A" (1) R/W "A" DATA IN "A" ADDR "B" DATA OUT "B" NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing ...

Page 10

... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 5. Timing depends on which enable signal (CE or R/W) is asserted last. Functional Description The IDT7134 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE ...

Page 11

... IDT7134SA/LA High-Speed Dual-Port Static SRAM Ordering Information IDT XXXX A 999 A Device Type Power Speed Package NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. ...

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