IDT71V016SA Integrated Device Technology, IDT71V016SA Datasheet
IDT71V016SA
Available stocks
Related parts for IDT71V016SA
IDT71V016SA Summary of contents
Page 1
... The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic FBGA. Row / Column Decoders Sense 16 64K x 16 Amps Memory and Write Array Drivers 1 IDT71V016SA/HSA I/O 15 High 8 8 Byte I/O Buffer I/O 8 I/O 7 Low 8 ...
Page 2
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Pin Configurations SO44 SO44 SOJ/TSOP Top View Truth Table ...
Page 3
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN OUT Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
Page 4
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Loads Z = 50Ω I/O 0 Figure 1. AC Test Load 7 6 ∆t t AA, ACS 5 (Typical, ns GND to 3.0V 1.5ns 1 ...
Page 5
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) AC Electrical Characteristics Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) Chip Select Low to Output in Low-Z t CLZ (1) Chip Select High to Output in High-Z t CHZ t Outp ut Enable Low to Output Valid ...
Page 6
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Timing Waveform of Read Cycle No. 2 ADDRESS OE CS BHE, BLE DATA OUT NOTES HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t 3. Transition is measured ±200mV from steady state. ...
Page 7
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) ADDRESS CS t BHE, BLE WE DATA OUT DATA IN NOTES write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. ...
Page 8
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Ordering Information IDT 71V016 Device Power Speed Package Type XXX X X Process/ Tape & Reel Temperature Range 6.42 8 Commercial and Industrial Temperature Ranges X 8 Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) Restricted hazardous ...
Page 9
... IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-bit) Datasheet Document History 1/7/00 Updated to new format Pp Added Industrial Temperature range offerings Pg. 2 Numbered I/Os and address pins on FBGA Top View Pg. 6 Revised footnotes on Write Cycle No. 1 diagram Pg. 7 Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Pg ...