IDT72255 Integrated Device Technology, Inc., IDT72255 Datasheet

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... Green parts available, see ordering information DESCRIPTION The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DESCRIPTION (CONTINUED) SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input ...

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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72255LA/72265LA are fabricated using IDT’s high speed submi- cron CMOS technology. PARTIAL RESET (PRS) ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10 0°C to +70°C; Industrial: VCC = 5V ± 10 –40°C to +85°C) Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK ...

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... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 8,193 writes for the IDT72255LA and 16,385 writes for the IDT72265LA, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72255LA/72265LA has internal registers for these offsets. Default set- tings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 72255LA — 8,192 x 18–BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, 3FFH HIGH at Master Reset 17 12 FULL OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, ...

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... words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 8,192 for the IDT72255LA and D = 16,384 for the IDT72265LA. In FWFT mode 8,193 for the IDT72255LA and D = 16,385 for the IDT72265LA. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that RT is setup. ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go after the valid WCLK cycle. HIGH after D writes to the FIFO (D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...

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... PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (8,192-m) writes for the IDT72255LA and (16,384-m) writes for the IDT72265LA. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1 ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW If FWFT = LOW HIGH t RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 6 ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES OCTOBER 17, 2005 ...

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... IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES OCTOBER 17, 2005 ...

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... FIFO after Master Reset more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 8,192 for IDT72255LA and 16,384 for IDT72265LA goes HIGH RCLK cycle + t REF ...

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... OR goes LOW RCLK cycles + t REF WCLK t ENS t LDS BIT 0 NOTE for the IDT72255LA and for the IDT72265LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW4 ENH t REF t HF ...

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... PAF offset maximum FIFO depth. In IDT Standard mode 8,192 for the IDT72255LA and 16,384 for the IDT72265LA. In FWFT mode 8,193 for the IDT72255LA and 16,385 for the IDT72265LA. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...

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... Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) WCLK D/2 words in FIFO [ + 1 RCLK NOTES: 1. For IDT Standard mode maximum FIFO depth. 2. For FWFT mode maximum FIFO depth 8,193 for the IDT72255LA and 16,385 for the IDT72265LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) (4) t PAE 2 t ENS , then the PAE deassertion may be delayed one extra RCLK cycle ...

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... OR of every FIFO, and separately ORing IR of every FIFO. Figure 23 demonstrates a width expansion using two IDT72255LA/ 72265LA devices D17 from each device form a 36-bit wide input bus and Q0-Q17 from each device form a 36-bit wide output bus. Any word width can be attained by adding additional IDT72255LA/72265LA devices ...

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... FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 24 shows a depth expansion using two IDT72255LA/72265LA devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next (" ...

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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device. 2. Green parts available. For specific speeds and packages contact your sales ...

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... DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin- for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences. ...