IDT72281 Integrated Device Technology, Inc., IDT72281 Datasheet
IDT72281
Available stocks
Related parts for IDT72281
IDT72281 Summary of contents
Page 1
... Industrial temperature range (-40°C to +85°C) is available DESCRIPTION: The IDT72281/72291 are exceptionally deep, high speed, CMOS First-In- First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • ...
Page 2
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 DESCRIPTION (CONTINUED) The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input ...
Page 3
... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72281/72291 are fabricated using IDT’s high speed submicron CMOS technology. PARTIAL RESET (PRS) ...
Page 4
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...
Page 5
... Unit COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Parameter Min. Typ. Max. 4.5 5.0 5 2.0 — — — — 0.8 0 — 70 -40 85 IDT72281 IDT72291 Commercial & Industrial ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — 80 — 20 Unit °C °C Unit µ ...
Page 6
... GND to 3.0V 3ns 1.5V * Includes jig and scope capacitances. 1.5V See Figure 2 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial & Industrial (2) IDT72281L15 IDT72281L20 IDT72291L15 IDT72291L20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — ...
Page 7
... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 65,537 writes for the IDT72281 and 131,073 writes for the IDT72291, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...
Page 8
... Empty Offset, Default Values 127 when parallel offset loading is selected 1,023 when serial offset loading is selected Full Offset, Default Values 127 when parallel offset loading is selected 1,023 when serial offset loading is selected. TABLE 2 — STATUS FLAGS FOR FWFT MODE IDT72281 Number of ...
Page 9
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 IDT72281 (65,536 x 9 BIT EMPTY OFFSET (LSB) REGISTER 7FH LOW at Master Reset FFH HIGH at Master Reset 8 7 EMPTY OFFSET (MSB) REGISTER 00H LOW at Master Reset 03H HIGH at Master Reset 8 7 FULL OFFSET (LSB) REGISTER ...
Page 10
... RCLK edges plus t The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q pins when LD is set LOW and REN is set LOW. For the IDT72281, data Q n are read via Q HIGH transition of RCLK ...
Page 11
... D– 2 words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 65,536 for the IDT72281 and D = 131,072 for the IDT72291 in IDT Standard mode. In FWFT mode 65,537 for the IDT72281 and D = 131,073 for the IDT72291 ...
Page 12
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...
Page 13
... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72281 and 131,073 for the IDT72291) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...
Page 14
... PAF will go LOW after (D – m) words are written to the FIFO. The PAF will go LOW after (65,536–m) writes for the IDT72281 and (131,072–m) writes for the IDT72291. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. In FWFT mode, the PAF will go LOW after (65,53– ...
Page 15
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t t RSS RSR t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...
Page 16
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF If FWFT = LOW HIGH t RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 6. Partial Reset Timing 16 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
Page 17
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...
Page 18
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
Page 19
... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...
Page 20
... FIFO after Master Reset more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72281 and 131,072 for the IDT72291 goes HIGH RCLK cycle + t . ...
Page 21
... FIFO after Master Reset goes LOW RCLK cycles + t REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72281 and for the IDT72291. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF PAF . ...
Page 22
... Figure 15. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291 t CLK t t CLKH CLKL RCLK t LDS LD t ENS REN DATA IN OUTPUT REGISTER NOTE LOW. Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281 t CLK t t CLKH CLKL RCLK t t LDS LDH ENS ENH REN ...
Page 23
... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 65,536 for the IDT72281 and 131,072 for the IDT72291. 2. For FWFT mode maximum FIFO depth 65,537 for the IDT72281 and 131,073 for the IDT72291. Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
Page 24
... ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 23 demonstrates a width expansion using two IDT72281/72291 devices. D each device form a 18-bit wide output bus. Any word width can be attained by adding additional IDT72281/72291 devices ...
Page 25
... Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72281 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72291 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
Page 26
ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. DATASHEET DOCUMENT HISTORY 04/24/2001 pgs and 26. CORPORATE HEADQUARTERS ...