IDT72V261LA Integrated Device Technology, IDT72V261LA Datasheet
IDT72V261LA
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IDT72V261LA Summary of contents
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... Industrial temperature range (–40 +85 available " " " " " DESCRIPTION: The IDT72V261LA/72V271LA are functionally compatible versions of the IDT72261/72271 designed to run off a 3.3V supply for very low power consumption. The IDT72V261LA/72V271LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency ...
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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by acti- vating control inputs) will immediately take the device out of the power down state. The IDT72V261LA/72V271LA are fabricated using IDT’s high speed submicron CMOS technology. PARTIAL RESET (PRS) MASTER RESET (MRS) ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN ...
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... Supply Voltage (Com’l/Ind’ Input High Voltage (Com’l/Ind’l) 2.0 ' Input Low Voltage (Com’l/Ind’ Operating Temperature 0 ' Commercial Operating Temperature 0 ' Industrial IDT72V261LA IDT72V271LA Commercial & Industrial ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V * Includes jig and scope capacitances. See Figure 1 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l (2) Commercial IDT72V261LA15 IDT72V261LA20 IDT72V271LA15 IDT72V271LA20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — ...
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... If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once the 8,193th word for IDT72V261LA and 16,385th word for IDT72V271LA respectively was written into the FIFO. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF LOW ...
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... VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V261LA/72V271LA has internal registers for these offsets. De- fault settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 IDT72V261LA ' 16,384 x 9 *+BIT 8 7 EMPTY OFFSET (LSB) REG. DEFAULT VALUE 07FH LOW at Master Reset 3FFH HIGH at Master Reset 8 5 EMPTY OFFSET (MSB) REG. 00H 8 7 FULL OFFSET (LSB) REG. ...
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... SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 28 bits for the IDT72V261LA and 30 bits for the IDT72V271LA. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 When EF goes HIGH, Retransmit setup is complete and read opera- tions may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...
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... When FF is HIGH, the FIFO is not full reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO (D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information ...
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... In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA. In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO, where D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS RSR t t RSS RSR t RSR t t RSR RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW HIGH t RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 6. Partial Reset Timing ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t ENH t ENS t RTS REN WCLK WEN t ENS RT EF PAE HF PAF 1 W x+1 t SKEW2 RTS t ENH t REF PAF Figure 11. Retransmit Timing (IDT Standard Mode) 20 COMMERCIAL AND INDUSTRIAL ...
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... OR goes LOW RCLK cycles + t . REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V261LA and for the IDT72V271LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF t HF ...
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... IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) t CLK t t CLKH CLKL ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA. 2. For FWFT mode maximum FIFO depth 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 21 demonstrates a width expansion using two IDT72V261LA/ 72V271LA devices from each device form a 18-bit wide input bus and Q0-Q8 from each device form a 18-bit wide output bus. Any word width can be attained by adding additional IDT72V261LA/72V271LA devices ...
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... VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V261LA can easily be adapted to applications requiring depths greater than 16,384 and 32,768 for the IDT72V271LA with a 9- bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. DATASHEET DOCUMENT HISTORY 04/25/2001 pgs. ...
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... DIFFERENCES BETWEEN THE IDT72V261LA/72V271LA AND IDT72V261L/72V271L IDT has improved the performance of the IDT72V261/72V271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences. ...