IDT72V283 Integrated Device Technology, Inc., IDT72V283 Datasheet

IDT72V283

Manufacturer Part Number

IDT72V283

Description

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72V283.pdf (45 pages)

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FEATURES:

•

• • • • •

FUNCTIONAL BLOCK DIAGRAM

*Available on the

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

BGA package only.

Choose among the following memory organizations:

IDT72V275/72V285 SuperSync FIFOs

Functionally compatible with the IDT72V255LA/72V265LA and

Up to 166 MHz Operation of the Clocks

User selectable Asynchronous read and/or write ports (BGA Only)

User selectable input and output port bus-sizing

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

- x18 in to x18 out

Pin to Pin compatible to the higher density of IDT72V2103/72V2113

Big-Endian/Little-Endian user selectable byte representation

5V tolerant inputs

Fixed, low first word latency

IDT72V223

IDT72V233

IDT72V243

IDT72V253

IDT72V263

IDT72V273

IDT72V283

IDT72V293

* *

ASYW

TRST

⎯ ⎯ ⎯ ⎯ ⎯

MRS

TMS

PRS

TCK

TDO

TDI

512 x 18/1,024 x 9

1,024 x 18/2,048 x 9

2,048 x 18/4,096 x 9

4,096 x 18/8,192 x 9

8,192 x 18/16,384 x 9

16,384 x 18/32,768 x 9

32,768 x 18/65,536 x 9

65,536 x 18/131,072 x 9

(BOUNDARY SCAN)

CONFIGURATION

WRITE CONTROL

WRITE POINTER

JTAG CONTROL

WEN

CONTROL

RESET

LOGIC

BUS

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO

512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9

2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9

8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9

32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9

WCLK/WR

OUTPUT REGISTER

65,536 x 18 or 131,072 x 9

16,384 x 18 or 32,768 x 9

32,768 x 18 or 65,536 x 9

8,192 x 18 or 16,384 x 9

1,024 x 18 or 2,048 x 9

2,048 x 18 or 4,096 x 9

4,096 x 18 or 8,192 x 9

INPUT REGISTER

512 x 18 or 1,024 x 9

-D

RAM ARRAY

-Q

(x9 or x18)

• • • • •

Zero latency retransmit

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable settings

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

Program programmable flags by either serial or parallel means

Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

JTAG port, provided for Boundary Scan function (BGA Only)

Independent Read and Write Clocks (permit reading and writing

simultaneously)

Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball

Grid Array (BGA) (with additional features)

High-performance submicron CMOS technology

Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available

Green parts available, see ordering information

OFFSET REGISTER

READ POINTER

LOGIC

CONTROL

FLAG

LOGIC

READ

SEN

RCLK/RD

REN

IDT72V223, IDT72V233

IDT72V243, IDT72V253

IDT72V263, IDT72V273

IDT72V283, IDT72V293

ASYR

PAF

EF/OR

PAE

FSEL1

FF/IR

FWFT/SI

PFM

FSEL0

4666 drw01

APRIL 2006

DSC-4666/15

Related parts for IDT72V283

IDT72V283 Summary of contents

Page 1

... OUTPUT REGISTER * Q -Q (x9 or x18 IDT72V223, IDT72V233 IDT72V243, IDT72V253 IDT72V263, IDT72V273 IDT72V283, IDT72V293 LD SEN OFFSET REGISTER FF/IR PAF EF/OR PAE FLAG HF LOGIC FWFT/SI PFM FSEL0 FSEL1 READ POINTER ...

Page 2

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION: The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are exceptionally deep, ...

Page 3

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 ...

Page 4

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION (CONTINUED) not have to be asserted ...

Page 5

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IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 PIN DESCRIPTION (TQFP & BGA PACKAGES) Symbol ...

Page 7

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... Input Low Voltage (Com'l & Ind'l) — Operating Temperature Commercial 0 Operating Temperature Industrial -40 = -40°C to +85°C; JEDEC JESD8-A compliant) A IDT72V223L IDT72V233L IDT72V243L IDT72V253L IDT72V263L IDT72V273L IDT72V283L IDT72V293L Commercial and Industrial ( 7-5, 10 CLK Min. Max. –1 1 –10 10 2.4 — — ...

Page 9

... A OE OHZ 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (2) Commercial TQFP Only IDT72V263L15 IDT72V273L15 IDT72V283L15 IDT72V293L15 Max. Min. Max. Unit 100 — 66.7 MHz (5) 6 — 15 — ns — 6 — ns — 6 — ns — ...

Page 10

... IDT72V263L6 IDT72V273L6 IDT72V283L6 IDT72V293L6 Min. — 0.6 10 4.5 4.5 8 — — — — 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com'l & Ind'l IDT72V223L7-5 IDT72V233L7-5 IDT72V243L7-5 IDT72V253L7-5 IDT72V263L7-5 IDT72V273L7-5 IDT72V283L7-5 IDT72V293L7-5 Max. Min. Max. Unit 100 — 83 MHz 8 0 — 12 — ns — 5 — ns — 5 — ...

Page 11

Page 12

... IDT72V233, 1,025th word for the IDT72V243, 2,049th word for the IDT72V253, 4,097th word for the IDT72V263, 8,193th word for IDT72V273, 16,385th word for the IDT72V283 and 32,769th word for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D the 513rd word for the ...

Page 13

... IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263, 16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537 writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, ...

Page 14

... IDT72V243 IDT72V253 n n+1 (n+2) to 1,025 (n+2) to 2,049 2,050 to (4,097-(m+1)) 1,026 to (2,049-(m+1)) (2,049-m) to 2,048 (4,097-m) to 4,096 1,025 2,049 IDT72V273 IDT72V283 IDT72V283 IDT72V293 n+1 (n+2) to 32,769 (n+2) to 16,385 16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1)) (32,769-m) to 32,768 (65,537-m) to 65,536 16,385 32,769 14 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FF PAF HF PAE EF ...

Page 15

... IDT72V263 13 bits for the IDT72V263 15 bits for the IDT72V273 14 bits for the IDT72V273 16 bits for the IDT72V283 15 bits for the IDT72V283 17 bits for the IDT72V293 16 bits for the IDT72V293 Note: All unused bits of the Note: All unused bits of the LSB & ...

Page 16

... IDT72V233 22 bits for the IDT72V243 24 bits for the IDT72V253 26 bits for the IDT72V263 28 bits for the IDT72V273 30 bits for the IDT72V283 32 bits for the IDT72V293 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) ...

Page 17

... So, a total of 18 bits for the IDT72V223, 20 bits for the IDT72V233, 22 bits for the IDT72V243, 24 bits for the IDT72V253, 26 bits for the IDT72V263, 28 bits for the IDT72V273, 30 bits for the IDT72V283 and 32 bits for the IDT72V293. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...

Page 18

... IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,024 for the IDT72V223, 2,048 for the ...

Page 19

Page 20

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This ...

Page 21

... IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the ...

Page 22

... Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the ...

Page 23

Page 24

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 MRS t RSS REN t RSS WEN ...

Page 25

Page 26

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K WRITE WCLK 1 t (1) SKEW1 ...

Page 27

Page 28

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K NARROW BUS FIFO COMMERCIAL AND INDUSTRIAL ...

Page 29

... If both x9 Input and x9 Output bus Widths are selected 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. ...

Page 30

... If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. ...

Page 31

Page 32

Page 33

... In FWFT mode: if x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...

Page 34

Page 35

... In IDT Standard mode maximum FIFO depth. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293 ...

Page 36

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 RCLK REN FFA WR ...

Page 37

Page 38

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K CYC t t CYH CYL WR ...

Page 39

Page 40

... IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...

Page 41

... Figure 31. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS (V = 3.3V CC IDT72V223 Parameter IDT72V233 IDT72V243 IDT72V253 JTAG Clock Input Period t IDT72V263 IDT72V273 JTAG Clock HIGH IDT72V283 IDT72V293 JTAG Clock Low Min. Max. Units JTAG Clock Rise Time - 20 ns JTAG Clock Fall Time JTAG Reset ns ...

Page 42

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 JTAG INTERFACE Five additional pins (TDI, TDO, ...

Page 43

Page 44

... Part Number field contains the following values: Device Part# Field IDT72V223 IDT72V233 IDT72V243 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IDT72V293 TM NARROW BUS FIFO 31(MSB) Version (4 bits) 0X0 IDT72V223/233/243/253/263/273/283/293 JTAG Device Identification Register JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state ...

Page 45

ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 2. The IDT72V223/72V233/72V243/72V253 are ...

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