IDT72V285 Integrated Device Technology, Inc., IDT72V285 Datasheet
IDT72V285
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IDT72V285 Summary of contents
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... INPUT REGISTER RAM ARRAY 32,768 x 18 65,536 x 18 OUTPUT REGISTER IDT72V275 IDT72V285 LD SEN OFFSET REGISTER FF/IR PAF EF/OR FLAG PAE LOGIC HF FWFT/SI READ POINTER READ RT CONTROL LOGIC RCLK ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 DESCRIPTION (Continued) The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 DESCRIPTION (Continued) These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN ...
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... Ind’l) 2.0 — Input Low Voltage (Com’l & Ind’l) — — Operating Temperature 0 — Commercial Operating Temperature -40 Industrial IDT72V275L IDT72V285L Com’’l & Ind’l ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 2 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l (2) Commercial IDT72V275L15 IDT72V275L20 IDT72V285L15 IDT72V285L20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — 6 — 8 — ...
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... Programmable Almost-Full flag (PAF LOW. Again reads are performed, the PAF will go LOW after (32,768-m) writes for the IDT72V275 and (65,536-m) writes for the IDT72V285. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 Figure 4, Programmable Flag Offset Programming Sequence, summa- rizes the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 72V275 (32,768 BIT EMPTY OFFSET REGISTER DEFAULT VALUE 007FH LOW at Master Reset, 03FFH HIGH at ...
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... words should have been written into the FIFO between SKEW2 Reset (Master or Partial) and the time of Retransmit setup 32,768 for the IDT72V275 and D = 65,536 for the IDT72V285. In FWFT mode 32,769 for the IDT72V275 and D= 65,537 for the IDT72V285. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MRS MRS MRS MRS) MASTER RESET (MRS A Master Reset ...
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... When FF is HIGH, the FIFO is not full reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO (D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing ...
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... PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (32,768-m) writes for the IDT72V275 and (65,536-m) writes for the IDT72V285. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 32,768 for IDT72V275 and 65,536 for IDT72V285 goes HIGH at 60ns + 1 RCLK cycle + t REF ...
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... OR goes LOW at 60ns + 2 RCLK cycles + t REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V275 and for the IDT72V285. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF ...
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... PAF offset . maximum FIFO depth. In IDT Standard mode 32,768 for the IDT72V275 and 65,536 for the IDT72V285. In FWFT mode 32,769 for the IDT72V275 and 65,537 for the IDT72V285. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 32,768 for the IDT72V275 and 65,536 for the IDT72V285. 2. For FWFT mode maximum FIFO depth 32,769 for the IDT72V275 and 65,537 for the IDT72V285. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V275 can easily be adapted to applications requiring depths greater than 32,768 and 65,536 for the IDT72V285 with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. ...
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IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO 32,768 x 18 and 65,536 x 18 • FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V275 72V285 n DATA IN Dn Figure 20. Block Diagram of 65,536 x 18 and ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. DATASHEET DOCUMENT HISTORY 04/24/2001 pgs and 25 CORPORATE HEADQUARTERS 6024 ...