IDT72V70200 Integrated Device Technology, IDT72V70200 Datasheet
IDT72V70200
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IDT72V70200 Summary of contents
Page 1
... Power Supply Operating Temperature Range - +85 C /GCI interfaces The IDT72V70200 is a non-blocking digital switch that has a capacity of 512 x 512 channels at 2.048 Mb/s. Some of the main features are: program- mable stream and channel control, Processor Mode, input offset delay and high- impedance output control. ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 INDEX RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE GND CLK VCC NOTES: 1. DNC - Do Not Connect Internal Connection, tie to GROUND for normal operation. ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 DNC DNC RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE/HCLK GND CLK VCC DNC DNC INDEX RX0 81 RX1 82 RX2 83 RX3 84 RX4 85 RX5 86 RX6 ...
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... This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V70200 is in the normal functional mode. Connect to GND for normal operation. This pin must be LOW for the IDT72V70200 to function normally and to comply with IEEE 1114 (JTAG) boundary scan requirements. ...
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... This data will be output on the TX streams in every frame until the data is changed by the microprocessor. As the IDT72V70200 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. ...
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... The same is true if input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 1 shows the possible delays for the IDT72V70200 in the variable delay mode. CONSTANT DELAY MODE (V/C BIT = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 CONNECTION MEMORY CONTROL The CCO pin is a 4.096 Mb/s output, which carries 512 bits. The contents of the CCO bit of each connection memory location are output on the CCO pin once every frame. The contents of the CCO bits of the connection memory are transmitted sequentially on to the CCO pin and are synchronous with the data rates on the other serial streams ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Control Register The Control Register is only accessed when A7-A0 are all zeroed. When A7 = bytes are randomly accessable via A0-A4 at any one instant. Of which stream these bytes (channels) are accessed is determined by the state - ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Delay for Variable Throughput Delay Mode Input Rate (m – output channel number) (n – input channel number) m < n+1, n+2 2.048 Mb/s 32 – (n-m) time-slots m time-slots m-n time-slots ( ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Read/Write Address Reset Value: 0000 . Bit Name 15-6 Unused Must be zero for normal operation. 5 MBP When 1, the connection memory block programming feature is ready for the programming of Connection (Memory Block Program) Memory high bits, bit 11 to bit 15 ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Read/Write Address Reset Value: 0000 . CFE FD11 FD10 Bit Name 15-13 Unused Must be zero for normal operation. 12 CFE When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Read/Write Address: 03 for FOR0 register for FOR1 register for FOR2 register for FOR3 register, H Reset Value: 0000 for all FOR registers OF32 OF31 OF30 DLE3 OF22 15 14 ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Input Stream Offset FD11 No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 V/C LPBK PC CCO OE Bit Name 15 LPBK (Per Channel Loopback) V/C 14 (Variable/Constant Throughput Delay (Processor Channel) 12 CCO (Control Channel Output (Output Enable) (1) 10-8,7 SAB3-0 (Source Stream Address Bits) (1) 6,5 Unused (1) 4-0 CAB4-0 (Source Channel Address Bits) NOTE: 1 ...
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... As specified in IEEE 1149.1, the IDT72V70200 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V70200 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Boundary Scan Bit 0 to bit 117 Device Pin Three-State Output Control Scan Cell TX7 0 TX6 2 TX5 4 TX4 6 TX3 8 TX2 10 TX1 12 TX0 14 ODE CCO 17 DTA D15 20 D14 23 D13 26 D12 29 D11 32 D10 AD7 ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Symbol Parameter V Supply Voltage CC Vi Voltage on Digital Inputs GND -0.3 I Current at Digital Outputs O T Storage Temperature S P Package Power Dissapation D NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Symbol Characteristics ® t Frame Pulse Width (ST-BUS FPW t Frame Pulse Setup time before CLK falling (ST-BUS FPS t Frame Pulse Hold Time from CLK falling (ST-BUS FPH t CLK Period CP t CLK Pulse Width HIGH ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 FPW F0i t FPS CLK (1) TX Bit 0, Last Ch RX (1) Bit 0, Last Ch NOTE: 1. last channel = ch 31. t FPW F0i t FPS CLK t SOD (1) TX Bit 7, Last Ch RX (1) Bit 7, Last Ch NOTE: 1. last channel = ch 31. CLK (ST-BUS or WFPS mode) ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Symbol Parameter t ALE Pulse Width ALW t Address Setup from ALE falling ADS t Address Hold from ALE falling ADH RD Active after ALE falling t ALRD Data Setup from DTA LOW on Read t DDR CS Hold after RD/WR t CSRW ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Symbol Parameter t ALE Pulse Width ASW t Address Setup from AS falling ADS t Address Hold from AS falling ADH Data Setup from DTA LOW on Read t DDR CS Hold after DS falling t CSH CS Setup from DS rising t CSS t Data Hold after Write ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 Symbol Parameter t CS Setup from DS falling CSS t R/W Setup from DS falling RWS t Address Setup from DS falling ADS t CS Hold after DS rising CSH t R/W Hold after DS Rising RWH t Address Hold after DS Rising ADH t Data Setup from DTA LOW on Read ...
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... IDT72V70200 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 CLK GCI CLK ST-BUS t DSS DS t CSS CS t RWS R/W t ADS A0-A7 AD0-AD7/ D8-D15 DTA t DSS t DSPW t t CSS CSH t t RWH RWS t t ADH ADS VALID READ VALID WRITE ADDRESS ADDRESS t t SWD DHW ...
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IDT XXXXXX XX Device Type Package 5/19/2000 pgs and 23. 8/15/2000 pgs and 23. 9/22/2000 pgs and 17. 1/04/2001 pgs. 6, 11, 17, 19, 20, 21 and 22. 1/25/2001 pgs. ...