lt3070 Linear Technology Corporation, lt3070 Datasheet
lt3070
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lt3070 Summary of contents
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... Output voltage is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070’s input. This tracking function drives the buck regulator to maintain the LT3070’s input voltage to V minimizing power dissipation. Internal protection includes UVLO, reverse-current protec- tion, precision current limiting with power foldback and thermal shutdown. The LT3070 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. ...
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... EN Input . ...................................................... –0. SENSE Input ................................................ –0. VIOC, PWRGD Outputs ................................ –0. REF/BYP Output . .......................................... –0. Output Short-Circuit Duration……...................Indefinite Operating Junction Temperature (Note 2) LT3070E/LT3070I .............................. –40°C to 125°C LT3070MP.......................................... –55°C to 125°C Storage Temperature Range . .................. –65°C to 150°C orDer inFormAtion LEAD FREE FINISH TAPE AND REEL ...
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... LT3070 MAX UNITS 3.0 V 3.6 V 0.808 V 0.909 V 1.010 V 1.111 V 1.212 V 1.515 V 1.818 V 1.2 % –0.8 % 3.3 % –2.7 % 5.4 % –4.6 % 1.0 mV 1.0 mV 2.0 mV 1.0 mV –3.0 mV –5.5 mV –4.0 mV – ...
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... LT3070 electricAl chArActeristics temperature range, otherwise specifications are at T otherwise noted. PARAMETER CONDITIONS BIAS Pin Current in Nap Mode EN = Low (After POR Completed) BIAS Pin Current 10mA OUT V = 1.3V 100mA IN OUT OUT I = 500mA OUT OUT I = 2.5A OUT OUT Current Limit (Note 5) V – – – ...
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... OUT ≤ 3.6V Note 8: Reverse output current is tested with the IN pins grounded and the BIAS OUT + SENSE pins forced to the rated output voltage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LT3070 must be frequency compensated at its OUT pins with a minimum cluster of (15×) 1µF ceramic capacitors graduated cluster of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear Technology only recommends X5R or X7R dielectric capacitors. LT3070 = V + 0.3V (Note 5 2.5V unless ...
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... LT3070 typicAl perFormAnce chArActeristics Dropout Voltage vs I OUT 150 OUT(NOMINAL 25°C J 120 1.8V OUT V = 3.3V BIAS 0.8V OUT V = 2.5V BIAS OUTPUT CURRENT (A) 3070 G01 Dropout Voltage vs Temperature 150 OUT(NOMINAL OUT 120 1.8V 3.3V OUT BIAS V = 0.8V 2.5V ...
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... V = 2.5V BIAS OUT 0.95 V RISING OUT 0.90 V FALLING OUT 0.85 0.80 175 –75 –50 – 100 125 TEMPERATURE (°C) LT3070 REF/BYP Pin Voltage vs Temperature 606 C = 0.01µF REF/BYP 604 602 600 598 = 3.3V 596 = 3.3V = 2.5V 594 4 5 –75 –50 – TEMPERATURE (°C) 3070 G11 ...
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... LT3070 typicAl perFormAnce chArActeristics Logic Input Threshold Voltages Logic Low to Hi-Z State Transitions 0.8 SEE APPLICATIONS INFORMATION FOR MORE DETAILS 0.7 INPUT RISING LOGIC LOW TO Hi-Z 0.6 INPUT FALLING 0.5 LOGIC Hi-Z TO LOW 0.4 0.3 –75 –50 – 100 125 150 175 TEMPERATURE (°C) 3070 G18 Logic Pin Input Current, ...
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... BIAS V = 2.1V 300 1.8V OUT I = 10mA 200 OUT 100 0 –100 –200 –300 –400 175 –75 –50 – 100 125 TEMPERATURE (°C) LT3070 IN Pin Ripple Rejection 117µF 30 OUT C = 16.9µF OUT OUT V = 1.3V + 50mV RIPPLE IN P 2.5V BIAS ...
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... LT3070 typicAl perFormAnce chArActeristics Input Voltage Line Regulation 300 V = 3.3V BIAS V = 2.05V TO 2.7V IN 250 V = 1.8V OUT I = 10mA OUT 200 150 100 50 0 –75 –50 – 100 125 150 TEMPERATURE (°C) 3070 G36 Output Noise Spectral Density 1 2.5V BIAS OUT OUT C = 16.9µ ...
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... TO 5A 3070 G46 20µs/DIV OUT C = 117µF OUT 100ns OUT RISE FALL Transient Load Response V OUT I OUT 2A/DIV TO 5A 3070 G49 20µs/DIV OUT C = 117µF OUT 1µs OUT RISE FALL LT3070 3070 G47 3070f ...
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... GND. To ensure proper electrical and thermal performance, solder Pin 29 to the PCB ground and tie to all GND pins of the package. These GND pins are fused to the internal die attach paddle and the exposed pad to optimize heat sinking and thermal resistance characteristics. See the Ap- plications Information section for thermal considerations and calculating junction temperature (Pins 8): Input Supply. These pins supply power to the high current pass transistor. Tie all IN pins together for proper performance. The LT3070 requires a bypass capacitor maintain stability and low input + impedance over frequency. A 47µF input bypass capacitor OUT suffices for most battery and power plane impedances. Minimizing input trace inductance optimizes performance. Applications that operate with low V voltages and that have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout ...
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... EN low keeps the reference circuit active, but disables the output pass transistor and puts the LT3070 into a low power nap mode. Drive the EN pin with either a digital logic port or an open-collector NPN or an open-drain NMOS terminated with a pull-up resistor to V resistor must be less than 35k to meet the V of the EN pin. If unused, connect EN to BIAS. LT3070 (Pins 23, 24, 25): Output Voltage Se- O2 when V = high. The input logic low O1 O2 – 250mV. The BIAS ...
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... LT3070 block DiAgrAm UVLO AND BIAS 27 THERMAL SHUTDOWN IN 5-8 – VIOC 1 + GND 4,9-14,20,26, MARGSEL OR MARGTOL REF/BYP + EAMP – BUF LDO CORE V + 300mV OUT(NOM) PROGRAM CONTROL LOGIC HIGH STATE – V – 0.25V BIAS + LOGIC Hi-Z STATE V BIAS + V – 0.9V ...
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... The LT3070’s features permit state-of-the-art linear regula- tor performance. The LT3070 is ideal for high performance FPGAs, microprocessors, sensitive communication sup- plies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3070 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator power- ing the LT3070’s input (see Figure 8). This tracking function drives the buck regulator to maintain the LT3070’ ...
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... O0 during an initial turn-on sequence. If the EN pin is toggled low after initial turn-on, the reference remains powered-up. Therefore, toggling the EN pin from low to high does not soft-start the reference. Only by turning the BIAS supply voltage on and off will the reference be soft-started. Output voltage noise is the RMS sum of the reference voltage noise in addition to the amplifier noise. The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3070 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. and O1 Output Voltage Margining Two tri-level input pins, MARGSEL (polarity) and MARGTOL = high. O2 (scale), select the polarity and amount of output voltage margining. Margining is programmable in increments of ± ...
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... Enable Function—Turning On and Off The EN pin enables/disables the output device only. The LT3070 reference and all support functions remain active above its UVLO threshold. Pulling the EN pin BIAS low puts the LT3070 into nap mode. In nap mode, the reference circuit is active, but the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an open- collector NPN or an open-drain NMOS terminated with a pull-up resistor The pull-up resistor must be BIAS less than 35k to meet the V condition of the EN pin ...
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... Low ESR, X5R or X7R ceramic chip capacitors are the LTC recommended choice for stabilizing the LT3070. Ad- ditional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic ESL and ESR, combined with the distributed PCB inductance on the rising isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. for more than The LT3070 requires a minimum output capacitance of 15µF for stability. LTC strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3070’s unity-gain bandwidth with C about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency 1/(2π ...
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... R mount ceramic capacitor manufacturer’s data sheets for capacitor specifications. Figure 3 illustrates an optimum PCB layout for the parallel output capacitor combination, but also illustrates the GND connection between the IN capacitor and the OUT capacitors to minimize the AC GND loop for fast load transients. This tight bypassing connection minimizes EMI and optimizes bypassing. Many of the applications in which the LT3070 excels, such as FPGA, ASIC processor or DSP supplies, typically require a high frequency decoupling capacitor network for the device being powered. This network generally consists of many low value ceramic capacitors in parallel. In some LT3070 SENSE IN OUT GND ...
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... TEMPERATURE (°C) Figure 5. Ceramic Capacitor Temperature Characteristics Stability and Input Capacitance The LT3070 is stable with a minimum capacitance of 47µF connected to its IN pins. Use low ESR capacitors to minimize instantaneous voltage drops under large load transient conditions. Large V droops during large load IN transients may cause the regulator to enter dropout with corresponding degradation in load transient response. Increased values of input and output capacitance may be necessary depending on an application’s requirements. ...
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... Under conditions of maximum the device’s power dissipation peaks at about IN OUT 3W. If ambient temperature is high enough, die junction temperature will exceed the 125°C maximum operating temperature. If this occurs, the LT3070 relies on two additional thermal safety features. At about 145°C, the PWRGD output pulls low providing an early warning of an impending thermal shutdown condition. At 165°C typically, the LT3070’s thermal shutdown engages and the output is shut down until the IC temperature falls below the thermal hysteresis limit. The SOA protection decreases current limit as the IN-to-OUT voltage increases and keeps the power dissipation at safe levels for all values of input-to-output voltage ...
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... The OUT of each LT3070 is connected to the common load using a small piece of PC trace as a ballast resistor (≅2mΩ actual sense resistor, beyond the primary output capacitors of each regulator. The ballast resistor ensures output current sharing (see Figures 8 and 9). The amount of ballast resistance used may need ...
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... SENSE LT3070 OUT 2.2µ MARGSEL *X5R OR X7R CAPACITORS NC MARGTOL VIOC REF/BYP GND 1nF 0.01µF 3070 F06 Figure 6. 1.5V to 1.2V Linear Regulator LT3070 from a reference current into an inter- REF = 1V. See the Typical Performance OUT . REF/BYP remains active in nap mode, thus start-up REF V OUT 1.2V 5A 4.7µF* 10µF* at the RMS 3070f ...
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... THM PGND SGND 2.2nF PGND PGND Figure 7. Regulator with VIOC Buck Control 50k PWRGD 2.2µF BIAS EN PWRGD SENSE IN 47µF OUT LT3070 2.2µF* 4.7µ *X5R OR X7R CAPACITORS NC MARGTOL NC MARGSEL VIOC REF/BYP GND 100pF 0.01µF 3070 F07 ...
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... OUT LT3070 2.2µF* 4.7µF* 10µ *X5R OR X7R CAPACITORS O2 MARGTOL MARGSEL VIOC REF/BYP GND 0.01µF 2.2µF BIAS EN PWRGD IN SENSE OUT LT3070 2.2µF* 4.7µF* 10µ *X5R OR X7R CAPACITORS O2 MARGTOL MARGSEL VIOC REF/BYP GND 0.01µF 3070 F08 V OUT 1V 3.5A R TRACE 3m CONTROLLED P ...
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... OUT O0 LT3070 2.2µF* V 4.7µ MARGTOL *X5R OR X7R CAPACITORS MARGSEL VIOC REF/BYP GND 0.01µF 2.2µF BIAS EN PWRGD SENSE IN OUT V O0 LT3070 2.2µF* V 4.7µ MARGTOL *X5R OR X7R CAPACITORS MARGSEL VIOC REF/BYP GND 0.01µF 3070 F09 V OUT TRACE 2m CONTROLLED P .O.L. 1 POWER ...
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... However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 0.05 3.65 0.05 PACKAGE OUTLINE 3.50 REF 4.10 0.05 5.50 0.05 0.75 0.05 4.00 0.10 (2 SIDES) 0.200 REF 0.00 – 0.05 LT3070 PIN 1 NOTCH 2.50 REF R = 0. 0.115 45 CHAMFER TYP TYP 27 28 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0506 REV B 0.25 0.05 0.50 BSC BOTTOM VIEW— ...
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... LT3070 relAteD pArts PART DESCRIPTION LT1761 100mA, Low Noise LDO LT1762 150mA, Low Noise LDO LT1763 500mA, Low Noise LDO LT1764/A 3A, Fast Transient Response, Low Noise LDO LTC ® 1844 150mA, Very Low Dropout LDO LT1962 300mA, Low Noise LDO LT1963/A 1.5A Low Noise, Fast Transient Response LDO LT1965 1.1A, Low Noise, Low Dropout Linear Regulator LT3020 100mA, Low Voltage VLDO™ Linear Regulator LT3021 500mA, Low Voltage, VLDO Linear Regulator LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µ ...