LTC2217 Linear Technology, LTC2217 Datasheet
LTC2217
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LTC2217 Summary of contents
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... The input range of the ADC is fi xed at 2.75V The LTC2217 is perfect for demanding communications applications, with AC performance that includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR) ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ................–0.3V to (OV Power Dissipation ............................................ 2000mW Operating Temperature Range LTC2217C ................................................ 0°C to 70°C LTC2217I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C Digital Output Supply Voltage (OV ORDER INFORMATION ...
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... Input 5MHz Input 15MHz Input 25°C A 15MHz Input 30MHz Input 70MHz Input 25°C A 70MHz Input 140MHz Input 5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input LTC2217 MIN TYP 2.75 ● 1.2 1.575 ● –1 ● – – 9.1 1.8 0.35 ...
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... LTC2217 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER S/(N+D) Signal-to-Noise www.datasheet4u.com Plus Distortion Ratio SFDR Spurious Free Dynamic Range at –25dBFS Dither “OFF” SFDR Spurious Free Dynamic Range at –25dBFS Dither “ON” IMD Intermodulation Distortion COMMON MODE BIAS CHARACTERISTICS full operating temperature range, otherwise specifi ...
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... 3. 1.60mA 3. –200μ 3. 1.60mA DD O 100Ω Differential Load 100Ω Differential Load 100Ω Differential Load 100Ω Differential Load LTC2217 MIN TYP MAX UNITS ● 0.2 V 1 Ω ● ● 0.8 V ● ...
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... LTC2217 POWER REQUIREMENTS range, otherwise specifi cations are at T SYMBOL PARAMETER V Analog Supply Voltage DD www.datasheet4u.com P Shutdown Power SHDN Standard LVDS Output Mode OV Output Supply Voltage DD I Analog Supply Current VDD I Output Supply Current OVDD P Power Dissipation DIS Low Power LVDS Output Mode ...
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... Note 7: Guaranteed by design, not subject to test. DD Note 8: Recommended operating conditions. without latchup P-P LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels – – – LTC2217 – – 3 2217 TD01 2217f 7 ...
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... LTC2217 TIMING DIAGRAMS www.datasheet4u.com ANALOG INPUT – ENC + ENC DA0-DA15, OFA CLKOUTA CLKOUTB DB0-DB15, OFB ANALOG INPUT – ENC + ENC DA0-DA15, OFA DB0-DB15, OFB CLKOUTA CLKOUTB 8 Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels ...
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... FREQUENCY (MHz) 2217 G07 LTC2217 Differential Nonlinearity (DNL) vs Output Code 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 65536 0 16384 32768 OUTPUT CODE 2217 G02 64k Point FFT 15.1MHz, IN – ...
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... LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point 2-Tone FFT 14.25MHz and 21.5MHz, IN –25dBFS, Dither “On” www.datasheet4u.com 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) SNR vs Input Level 15.2MHz –80 –70 –60 –50 –40 –30 –20 –10 ...
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... FREQUENCY (MHz) 2217 G25 LTC2217 SFDR vs Input Level 70.5MHz, Dither “On” IN 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 ...
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... LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Level 140.5MHz, Dither “Off” www.datasheet4u.com IN 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) SFDR (HD2 and HD3) vs Input Frequency 110 105 100 95 HD2 ...
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... WAKE-UP 0.3 0.2 0.1 0.0 CLOCK START –0.1 –0.2 –0.3 –0.4 –0 300 600 900 TIME AFTER WAKE-UP OR CLOCK START (μs) 2217 G41 LTC2217 – TEMPERATURE (°C) 2217 G38 – TEMPERATURE (°C) 2217 G40 Full-Scale Settling After Wake Up from Shutdown or Starting Encode Clock 0 ...
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... LTC2217 PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External www.datasheet4u.com Reference Input. Tie SENSE to V 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.75V. GND (Pins 10, 11, 14, 18): ADC Power Ground. ...
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... NC (Pin 64): Not Connected Internally. For pin compat- ibility with the LTC2208 this pin should be connected to GND or V GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be sol- dered to ground. LTC2217 – + /CLKOUT (Pins 39 and 40): LVDS Data Valid – ...
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... LTC2217 BLOCK DIAGRAM + A IN www.datasheet4u.com INPUT FIRST PIPELINED S/H ADC STAGE – DITHER SIGNAL GENERATOR RANGE SELECT SENSE V CM BUFFER VOLTAGE REFERENCE 16 SECOND PIPELINED THIRD PIPELINED ADC STAGE ADC STAGE ADC CLOCKS DIFFERENTIAL ADC INPUT PGA REFERENCE LOW JITTER CLOCK DRIVER + – ...
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... This random variation will result in noise when sampling an AC input. The signal-to-noise ratio term due to the jitter alone will be: SNR This formula states SNR due to jitter alone at any amplitude in terms of dBc. LTC2217 + equals the ENC = –20log (2π • f • ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2217 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (C through NMOS transitors. The capacitors shown attached to each input (C capacitance associated with each input ...
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... Transformer Coupled Circuits Figure 3 shows the LTC2217 being driven trans- former with a center-tapped secondary. The secondary center tap is DC biased with V signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used ...
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... ADC input. Reference Operation Figure 6 shows the LTC2217 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain ampli- fi er and control circuit. The LTC2217 has three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal 20 ...
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... Figure 7. A 2.75V Range ADC with an External 2.5V Reference Driving the Encode Inputs The noise performance of the LTC2217 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources ...
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... PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/ The lower limit of the LTC2217 sample rate is determined + ENC by droop affecting the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog – LTC2217 ENC signals on small valued capacitors ...
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... DD 43Ω TYPICAL Data Format DATA OUTPUT The LTC2217 parallel digital output can be selected for offset binary or 2’s complement format. The format is OGND selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3V 2217 F11 external resistor divider can be user to set the 1/3V and 2/3V for the MODE pin ...
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... To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the 24 LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high. LTC2217 CLKOUT OF D15 D14 D2 ...
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... Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit Internal Dither FPGA The LTC2217 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches ...
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... The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2217 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board critical that the exposed pad and all ground pins are connected to a ground plane of suffi ...
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... APPLICATIONS INFORMATION www.datasheet4u.com Layer 1 Component Side LTC2217 Layer 2 GND Plane 2217f 27 ...
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... LTC2217 APPLICATIONS INFORMATION www.datasheet4u.com Layer 3 GND 28 Layer 4 GND 2217f ...
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... APPLICATIONS INFORMATION www.datasheet4u.com Layer 5 GND LTC2217 Layer 6 Bottom Side 2217f 29 ...
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... LTC2217 APPLICATIONS INFORMATION www.datasheet4u.com VC5 48 VC4 47 VC3 26 VC2 25 VC1 12 • • 30 VE5 VC5 37 48 VE4 VC4 36 47 VE3 VC3 23 26 VE2 VC2 2 25 VE1 VC1 OVDD49 OVDD32 49 32 OGND50 OGND31 50 31 D12– D4 D12+ D4– D13– D3+ ...
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... Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0. 0.10 TYP 7.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2217 R = 0.115 TYP 63 64 PIN 1 CHAMFER C = 0.35 7.15 ± 0.10 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 31 0.40 ± 0.10 ...
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... LTC2217 RELATED PARTS PART NUMBER DESCRIPTION LTC1749 12-Bit, 80Msps Wideband ADC www.datasheet4u.com LTC1750 14-Bit, 80Msps Wideband ADC LT1993 High Speed Differential Op Amp LTC2202 16-Bit, 10Msps ADC LTC2203 16-Bit, 25Msps ADC LTC2204 16-Bit, 40Msps ADC LTC2205 16-Bit, 65Msps ADC LTC2206 16-Bit, 80Msps ADC ...