LTC2249 Linear Technology, LTC2249 Datasheet
LTC2249
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LTC2249 Summary of contents
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... CLK DataSheet4U.com DESCRIPTIO The LTC converter designed for digitizing high frequency, wide dynamic range signals. The LTC2249 is perfect for de- manding imaging and communications applications with AC performance that includes 73dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. Range P-P DC specs include ± ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ................ –0.3V to (OV Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2249C ............................................... 0°C to 70°C LTC2249I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C U ...
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... Input 70MHz Input 140MHz Input 5MHz Input 40MHz Input 70MHz Input 140MHz Input f = 28.2MHz, f IN1 Figure 8 Test Circuit DataSheet4U.com U CONDITIONS OUT 2.7V < V < 3.4V DD –1mA < I < 1mA OUT LTC2249 MIN TYP 73 ● 70 72.6 90 ● ● 72.9 ● ...
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... LTC2249 U DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER LOGIC INPUTS (CLK, OE, SHDN) V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN C Input Capacitance IN LOGIC OUTPUTS Hi-Z Output Capacitance ...
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... DD with differential Note 8: V P-P differential drive. DataSheet4U.com Note 9: Recommended operating conditions Typical DNL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 16384 8192 0 4096 CODE 2249 G01 LTC2249 MIN TYP ● 1 ● 5.9 6.25 ● 5 6.25 ● 5.9 6.25 ● 5 6.25 0 ● 1.4 2.7 ● 4.3 ● 80MHz, input range = 1V ...
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... LTC2249 TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT 30MHz, IN –1dB, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 8192 Point 2-Tone FFT 28.2MHz and 26.8MHz, IN –1dB, 2V Range 0 –10 –20 –30 – ...
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... GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connect- ing SHDN to GND and OE to GND results in normal LTC2249 SFDR vs Input Level 70MHz, 2V Range IN 120 ...
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... LTC2249 CTIO S operation with the outputs enabled. Connecting SHDN to GND and results in normal operation with the DD outputs at high impedance. Connecting SHDN GND results in nap mode with the outputs at high impedance. Connecting SHDN to V results in sleep mode with the outputs at high impedance. ...
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... RMS value of a full scale input signal )/V1 Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal – – – 1 2249 TD01 LTC2249 2249f 9 ...
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... SNR = –20log (2π) • f JITTER CONVERTER OPERATION As shown in Figure 1, the LTC2249 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value six cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2249 being driven transformer with a center tapped secondary. The second- ary center tap is DC biased with V signal at its optimum DC level. Terminating on the trans- ...
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... A IN 2249 F05 Reference Operation Figure 9 shows the LTC2249 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage refer- ence can be configured for two pin selectable input ranges of 2V (±1V differential (±0.5V differential). Tying the ...
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... CONTROL BUFFER INTERNAL ADC HIGH REFERENCE The noise performance of the LTC2249 can depend on the clock signal quality as much as on the analog input. Any DIFF AMP noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter ...
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... LTC2249 U U APPLICATIO S I FOR ATIO The lower limit of the LTC2249 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating fre- quency for the LTC2249 is 1Msps ...
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... Hi-Z state. Grounding and Bypassing The LTC2249 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an inter- nal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible ...
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... LTC2249 U U APPLICATIO S I FOR ATIO DataSheet4U.com DataSheet4U.com 2249f ...
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... U U APPLICATIO S I FOR ATIO Silkscreen Top DataSheet4U.com W U DataSheet4U.com Inner Layer 2 GND LTC2249 Topside 2249f 17 ...
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... LTC2249 U U APPLICATIO S I FOR ATIO Inner Layer 3 Power DataSheet4U.com DataSheet4U.com Silkscreen Bottom Bottomside 2249f ...
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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC2249 BOTTOM VIEW—EXPOSED PAD R = 0.115 ...
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... LTC2249 RELATED PARTS PART NUMBER DESCRIPTION LTC1741 12-Bit, 65Msps ADC LTC1742 14-Bit, 65Msps ADC LTC1743 12-Bit, 50Msps ADC LTC1744 14-Bit, 50Msps ADC LTC1745 12-Bit, 25Msps ADC LTC1746 14-Bit, 25Msps ADC LTC1747 12-Bit, 80Msps ADC LTC1748 14-Bit, 80Msps ADC LTC1749 12-Bit, 80Msps Wideband ADC ...