LTC2424 Linear Technology, LTC2424 Datasheet
LTC2424
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LTC2424 Summary of contents
Page 1
... The first conversion after the channel is changed is always valid. Through a single pin the LTC2424/ LTC2428 can be configured for better than 110dB rejec- tion at 50Hz or 60Hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 800Hz ...
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... Full-Scale Error 2.5V V Full-Scale Error (Fast Mode) 2.5V < V Full-Scale Error Drift 2. RATINGS Operating Temperature Range LTC2424C/LTC2428C .............................. 0.3V 0.3V) LTC2424I/LTC2428I ........................... – 0.3V) Storage Temperature Range ................. – 150 0.3V) Lead Temperature (Soldering, 10 sec).................. 300 ORDER PART NUMBER 1 GND ...
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... 1.5V 3.4k 15pF 1.5V 3.4k 15pF 1k 100kHz IN P 1000pF LTC2424/LTC2428 MIN TYP MAX UNITS 8 ppm of V REF 16 ppm of V REF 6 V RMS 20 V RMS 110 130 dB 110 130 dB 100 dB 110 dB 110 dB MIN TYP ...
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... LTC2424/LTC2428 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH CS Low Level Input Voltage IL CS High Level Input Voltage IH SCK V Low Level Input Voltage IL SCK I Digital Input Current ...
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... V rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V 0.267V + 0.89 • V For 0.267V + 0.89 • 153600Hz 0.3V. CC Note 15 128000Hz 2% applied to the MUX output. Note 16: V CC(DC) LTC2424/LTC2428 MIN TYP MAX 2.56 307.2 2.56k 2.048M 0.5 390 0.5 390 130.66 133.33 136 156 ...
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... CH6 (Pin 15): Analog Multiplexer Input. No connect on the LTC2424. CH7 (Pin 17): Analog Multiplexer Input. No connect on the LTC2424. CLK (Pin 19): Shift Clock for Data In. This clock synchro- nizes the serial data transfer into the MUX. For normal operation, drive this pin in parallel with SCK. ...
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... By tying SCK to CLK and CSADC to CSMUX, the IN interface requires only four wires. Initially, the LTC2424 or LTC2428 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CSADC is logic HIGH ...
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... LTC2428 reject line frequencies (50 or 60Hz 2%) a minimum of 110dB. is all 0’s, the Ease of Use IN The LTC2424/LTC2428 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. ...
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... V 5V. This error has a very strong temperature dependency. Output Data Format The LTC2424/LTC2428 serial output data stream is 24 bits long. The first 4 bits represent status information indicat- ing the sign, input range and conversion state. The next 20 bits are the conversion result, MSB first ...
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... U APPLICATIONS INFORMATION CSADC SCK SDO EOC = 1 CONVERSION Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408 Bit 20 (forth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range this bit is LOW. If the input is outside the IN REF normal input range, V > ...
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... U U APPLICATIONS INFORMATION CSMUX/CSADC SDO Hi-Z SCK/CLK Table 2. LTC2424/LTC2428 Output Data Format Bit 23 Bit 22 Input Voltage EOC DMY V > 9/8 • REF 9/8 • REF V + 1LSB 0 0 REF REF 3/4V + 1LSB 0 0 REF 3/ REF 1/2V + 1LSB 0 0 REF 1/ REF ...
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... Whenever an external clock is not present at the F converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2424/LTC2428 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the Table 4 ...
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... As shown in Figure 8, for output data rates of 100 samples/second, the TUE is better than 15 bits for V unaveraged total unadjusted error for the LTC2424 or LTC2428 operating at 100 samples/second with V 2.5V. Figure 10 shows the same device operating with a 5V reference and an output data rate of 7.5 samples/second. ...
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... Figure 10. Total Unadjusted Error at 7.5 Samples/Second (No Averaging) At 100 samples/second, the LTC2424/LTC2428 can be used to capture transient data. This is useful for monitor- ing settling or auto gain ranging in a system. The LTC2424/ LTC2428 can monitor signals at an output rate of 100 samples/second. After acquiring 100 samples/second data, the F ...
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... TIME (SEC) Figure 12c. Digitized Waveform with No Offset Figure 12. Using the LTC2424/LTC2428’s High Accuracy Wide Dynamic Range to Digitize a 300mV floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode ...
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... IN on the previously selected channel. SERIAL INTERFACE TIMING MODES The LTC2424/LTC2428’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers two modes of operation. These include an internal or external serial clock. The following sections describe both of these serial interface timing modes in detail. For both cases the ...
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... Internal Serial Clock This timing mode uses an internal serial clock to shift out the conversion result and program the multiplexer, see Figure 16 signal directly drives the CSADC input, while the inverse of CS drives the CSMUX input. The CS LTC2424/LTC2428 50Hz REJECTION = EXTERNAL OSCILLATOR ...
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... CSADC. An internal weak pull- BIT22 BIT21 BIT20 BIT19 BIT18 BIT4 BIT0 SIG EXR MSB LSB DON’T CARE DATA OUTPUT 2. LTC2424/LTC2428 0.1V FS CSMUX SET CSADC –0.12V CH0 REF TO 1.12V TO CH7 SCK REF MUXOUT CLK ADCIN ...
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... Table 3. On the rising edge of CSADC (falling edge of EOCtest CSMUX), the new channel is selected and will be valid for the next conversion output state, the previous channel selection remains valid. LTC2424/LTC2428 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION ...
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... U mode. However, certain applications may require an exter- nal driver on SCK. If this driver goes HI-Z after outputting a LOW signal, the LTC2424/LTC2428’s internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CSADC, the device is switched to the external SCK timing mode. By adding an external 10k pull- up resistor to SCK, this pin goes HIGH once the external driver goes HI-Z ...
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... Parallel termination near the LTC2424/LTC2428 input pins will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2424/LTC2428 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology ...
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... ANTIALIASING One of the advantages delta-sigma ADCs offer over con- ventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2424/LTC2428 signifi- cantly simplify antialiasing filter requirements. The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (f ), see Figure 21 ...
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... As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2424/LTC2428. If passive RC components are placed in front of the LTC2424/LTC2428, the input dy- namic current should be considered. In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current ...
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... LTC2424/LTC2428 U U APPLICATIONS INFORMATION Gain can be added to this circuit as the total voltage drop across all the RTDs is small compared to ADC full-scale range. The maximum recommended gain is 50, as limited by both amplifier noise contribution, as well as the maxi- mum voltage developed at CH0 when all sensors are at the maximum temperature specified for platinum RTDs ...
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... ADCIN FS 9 CH0 10 CH1 11 CH2 12 CH3 20-BIT 8-CHANNEL + ADC 13 CH4 MUX 14 CH5 – 15 CH6 17 CH7 LTC2428 5 ZS SET GND 1, 6, 16, 18, 22, 27, 28 LTC2424/LTC2428 5V 0. SET CC 23 CSADC 20 CSMUX 25 20-BIT SCK + ADC 19 CLK 21 D – SDO V LTC2428 ...
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... LTC2424/LTC2428 U U APPLICATIONS INFORMATION use of single-ended arrangements. In those applications where differential signal conditioning is required, chopper amplifier-based or self-contained instrumentation ampli- fiers (also available from LTC) can be used with the LTC2428. With the resistor network connected to CH0, the LTC2428 is able to measure DC voltages from 1mV to 1kV in a single range without the need for autoranging ...
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... BSC 0.25 – 0.38 (0.010 – 0.015) LTC2424/LTC2428 at 960nM (direct sunlight is approximately 2 ) can be measured by the LTC2428. With a ADC. Very low level 10.07 – 10.33* (0.397 – 0.407 7.65 – 7.90 (0.301 – 0.311) ...
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... Max Initial Accuracy, 5ppm/ C Drift 50 A, 0.04%, 3ppm/ C Drift 10pA Max Input Bias Current, Low Voltage Noise: 8nV <4ppm INL, No Missing Codes, 4ppm Full Scale < 4ppm INL, No Missing Codes, Interchangeable with the LTC2424/LTC2428 grounded SET 24248f LT/TP 0300 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2000 ...